Leakage in Nanometer CMOS Technologies pp 105-140 | Cite as
Body Biasing
Chapter
Keywords
Leakage Current Leakage Power Standby Mode Substrate Contact PMOS Device
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Preview
Unable to display preview. Download preview PDF.
References
- [1]T. Kuroda and T. Sakurai, “Overview of Low-Power ULSI Circuit Techniques,” IEICE Trans. Electron., vol. E78-C, no. 4, pp. 334–344, Apr. 1995.Google Scholar
- [2]A. P. Chandrakasan and R. W. Brodersen, “Low Power Digital CMOS Design,” Kluwer Academic Publishers, 1995.Google Scholar
- [3]A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, Piscataway, NJ, 2001.Google Scholar
- [4]M. Pedram and J. Rabaey, Power Aware design Methodologies, Kluwer Academic Publishers, 2002.Google Scholar
- [5]P. Maxwell, R. Aitken, K. Kollitz, and A. Brown, “IDDQ and ac scan: the war against unmodelled defects,” Proc. Int. Test Conf., pp. 250–258, Nov. 1996.Google Scholar
- [6]S-W. Sun and P. G. Y. Tsui, “Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 947–949, Aug. 1995.CrossRefGoogle Scholar
- [7]T. Kuroda and T. Sakurai, “Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design,” J. VLSI Signal Processing Systems, Kluwer Academic Publishers, vol.13, no. 2/3, pp. 191–201, Aug./Sep. 1996.CrossRefGoogle Scholar
- [8]T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, “A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1770–1779, Nov. 1996.CrossRefGoogle Scholar
- [9]T. Kobayashi and T. Sakurai, “Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation,” Proc. CICC’94, pp. 271–274, May 1994.Google Scholar
- [10]K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, “50% active-power saving without speed degradation using standby power reduction (SPR) circuit,” 1SSCC Dig. Tech. Papers, pp. 318–319, Feb. 1995.Google Scholar
- [11]T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai, “A high-speed low-power 0.3um CMOS gate array with variable threshold voltage (VT) scheme,” Proc. CICC’96, pp. 53–56, May 1996.Google Scholar
- [12]T. Kuroda, T. Fujita, S. Mita, T. Mori, K. Matsuo, M. Kakumu, and T. Sakurai, “Substrate noise influence on circuit performance in variable threshold-voltage scheme,” Proc. ISLPED’96, pp. 309–312, Aug. 1996.Google Scholar
- [13]R. D. Pashley and G. A. McCormick, “A 70-ns 1K MOS RAM,” ISSCC Dig. Tech. Papers, pp. 138–139, Feb. 1976.Google Scholar
- [14]H. Makino, Y. Tsujihashi, K. Nii, C. Morishima, Y. Hayakawa, T. Shimizu, and T. Arakawa, “An auto-backgate-controlled MT-CMOS circuit,” Symposium on VLSI Technology Dig. Tech. Papers, pp. 42–43, June 1998.Google Scholar
- [15]M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, Y. Tsuboi, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terasawa, F. Sano, Y. Watanabe, H. Momose, K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, T. Kuroda, and T. Furuyama, “A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme,” ISSCC Dig. Tech. Papers, pp. 34–35, Feb. 1998.Google Scholar
- [16]K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, “Design Impact of Positive Temperature Dependence of Drain Current in Sub IV CMOS VLSI’s,” Proc. CICC’99, pp. 563–566, May 1999.Google Scholar
- [17]H. Kirsch, D. Clemons, S. Davar, J. Harman, C. Holder, W. Hunsicker, F. Procyk, J. Stefany, and D. Yaney, “A 1Mb CMOS DRAM,” ISSCC Dig. Tech. Papers, pp. 256–257, Feb. 1985.Google Scholar
- [18]T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584–594, Apr. 1990.CrossRefGoogle Scholar
- [19]A. Keshavarzi, S. Narendra, S. Borkar, C. Hawkins, K. Royi, and V. De, “Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s,” Proc. Low Power Electronics and Design, pp. 252–254, Aug. 1999.Google Scholar
- [20]A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, “Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs,” Proc. Low Power Electronics and Design, pp. 207–212, Aug. 2001.Google Scholar
- [21]M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T. Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, and K. Imai, “Power-aware 65nm node CMOS technology using variable VDD and back-bias control with reliability consideration for back-bias mode,” Symposium on VLSI Technology Dig. Tech. Papers, pp. 88–89, June 2004.Google Scholar
- [22]S. Narendra, A. Keshavarzi, B.A. Bloechel, S. Borkar, and V. De, “Forward body bias for microprocessors in 130-nm technology generation and beyond,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 696–701, May 2003.CrossRefGoogle Scholar
- [23]S. Narendra, M. Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson, S. Vangal, A. Pangal, E. Seligman, R. Nair, A. Keshavarzi, B. Bloechel, G. Dermer, R. Mooney, N. Borkar, S. Borkar, and V. De, “1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS,” ISSCC Dig. Tech. Papers, pp. 270–271, Feb. 2002.Google Scholar
- [24]S. Vangal, M.A. Anders, N. Borkar, E. Seligman, V. Govindarajulu, V. Erraguntla, H. Wilson, A. Pangal, V. Veeramachaneni, J. Tschanz, Y. Ye, D. Somasekhar, B. Bloechel, G. Dermer, R.K. Krishnamurthy, K. Soumyanath, S. Mathew, S. Narendra, M. Stan, S. Thompson, V. De, and S. Borkar, “5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1421–1432, Nov. 2002.CrossRefGoogle Scholar
- [25]H. Banba, H. Shiga, A. Umezawa, T. Miyabe, T. Tanzawa, S. Atsumi, and K. Sakui, “A CMOS band-gap reference circuit with sub-lV operation,” Symposium on VLSI Circuits Dig. Tech. Papers, pp. 228–229, June 1998.Google Scholar
- [26]H. Kawaguchi, Y. Itaka and T. Sakurai, “Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM’s,” Symposium on VLSI Circuits Dig. Tech. Papers, pp.140–141, June 1998.Google Scholar
- [27]J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antonladls, A. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of doe-to-deiand within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1396–1402, Nov. 2002.CrossRefGoogle Scholar
- [28]K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakurai, “VTH-hopping scheme to reduce sub-threshold leakage for low-power processors,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 413–419, Mar. 2002.CrossRefGoogle Scholar
- [29]M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, “A 100-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias,” ISSCC Dig. Tech. Papers, pp. 420–421, Feb. 2000.Google Scholar
- [30]G. Ono and M. Miyazaki, “Threshold-voltage balance for minimum supply operation,” Symposium on VLSI Circuits Dig. Tech. Papers, pp. 206–209, June 2002.Google Scholar
- [31]K. Ishibashi, T. Yamashita, Y. Arima, I. Minematsu, and T. Fujimoto, “A 9μW 50MHz 32b adder using a self-adjusted forward body bias in SoCs,” ISSCC Dig. Tech. Papers, pp. Paper#6.8, Feb. 2003.Google Scholar
Copyright information
© Springer Science+Business Media, Inc. 2006