Testing Strategies for Networks on Chip

  • Raimund Ubar
  • Jaan Raik

Abstract

The complexity of Networks-on-Chip (NoC) makes the application of traditional test methods obsolete. For NoC, a combination of methods known from the System-on-Chip, memory and FPGA test areas should be used. That includes functional test, scan test, logic BIST, RAM BIST and testing of interconnect switches and wires. The increasing complexities of systems based on deep-submicron technologies cause two contrary trends: low-level defect-orientation to reach the high reliability of testing and high-level behavioral modeling to reach the efficiency of test generation. Hierarchical approaches seem to be the solution. Built-in Self-Test (BIST) is the main concept for testing the cores in systems on chip. Hybrid BIST containing both hardware and software components is probably the most promising approach to test the nodes of NoC. In densely packaged NoC with embedded memories and reusable cores scan-based approaches, P1500 standard for core test, test access mechanisms, test control and isolation issues are prospective methods. Testing the NoC interconnect switches and wires is also an important issue.

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References

  1. [1]
    T. W. Williams and N. C. Brown, “Defect Level as a Function of Fault Coverage”, IEEE Trans. on Computers, Vol. C-30, No. 12, pp. 987–988, 1981.Google Scholar
  2. [2]
    A.J. van de Goor. Testing Semiconductor Memories. J.Wiley & Sons, 1991, 512 p.Google Scholar
  3. [3]
    S.M. Thatte, J.A. Abraham. Test Generation for Microprocessors. IEEE Trans. On Computers, 1980, Vol. C-29, No. 6, pp.429–441.MathSciNetGoogle Scholar
  4. [4]
    P. Nigh, W. Maly. Layout-Driven Test Generation. Proc.1989 ICCAD, pp. 154–157, 1989.Google Scholar
  5. [5]
    M. Jacomet, W. Guggenbuhl. Layout-Dependent Fault Analysis and Test Synthesis for CMOS Circuits. IEEE Trans. on CAD, vol. 12, pp. 888–899, 1993.Google Scholar
  6. [6]
    R. Ubar, W. Kuzmicz, W. Pleskacz, J. Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Proc. ISQED, San Jose, March 26–28, 2001, pp.365–371.Google Scholar
  7. [7]
    S.R. Rao, B.Y. Pan, J.R. Armstrong. Hierarchical Test Generation for VHDL Behavioral Models. EDAC, Feb. 1993, pp. 175–183.Google Scholar
  8. [8]
    J. Raik, R. Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213–226, 2000.Google Scholar
  9. [9]
    E. M. Rudnick, J. H. Patel, G. S. Greenstein, T. M. Niermann, “Sequential Circuit Test Generation in a Genetic Algorithm framework,” Proc. DAC, pp. 698–704, 1994.Google Scholar
  10. [10]
    T.M. Niermann, J.H. Patel, “HITEC: A test generation package for sequential circuits”, Proc. of EDAC, 1991, pp.214–218.Google Scholar
  11. [11]
    M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer Science Press, 1995, 653 p.Google Scholar
  12. [12]
    P. Bardell, et. al. Built-in Test for VLSI Pseudorandom Techniques. Wiley & Sons, 1987.Google Scholar
  13. [13]
    E.J. McCluskey. Logic Design Principles: With Emphasis on Testable Semicustom Circuits. Prentice Hall, 1986.Google Scholar
  14. [14]
    E.B. Eichelberger, E. Lindbloom, J.A. Waicucauski, T.W. Williams. Structured Logic Testing. Prentice Hall, 1991, 183 p.Google Scholar
  15. [15]
    S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois. Generation of Vector Patterns through Receeding a Multiple-Polynomial LFSR. Proc. ITC, Baltimore, 1992, pp.120–129.Google Scholar
  16. [16]
    N.A. Touba, E.J. McCluskey. Altering a Pseudorandom Bit Sequence for Scan-Based BIST. Proc. IEEE Int. Test Conference, 1996, pp.167–175.Google Scholar
  17. [17]
    H.J. Wunderlich, G. Kiefer. Scan-Based BIST with Complete Fault Coverage and Low Hardware Overhead. Proc. IEEE European Test Workshop, pp.60–64.Google Scholar
  18. [18]
    J. Rajski, J. Tyszer. Arithmetic BIST For Embedded Systems, Prentice-Hall, 1998.Google Scholar
  19. [19]
    R. Dorsch, H.-J. Wunderlich. Accumulator Based Deterministic BIST, Proceedings IEEE International Test Conference, Washington, DC, October 1998, 412–421.Google Scholar
  20. [20]
    R.A. Frohwerk. Signature Analysis: A New Digital Field Service Method. Hewlett-Packard Journal, 1977, Vol.28, No. 9, pp.2–8.Google Scholar
  21. [21]
    S. Mourad, Y. Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc. New York, 2000, 420 p.Google Scholar
  22. [22]
    J.J. LeBlanc. LOCST: A Built-in Self-Test Technique. IEEE Design and Test of Computers, November, 1984, pp.42–52.Google Scholar
  23. [23]
    A. Krasniewski, S. Pilarski. Circular self-test path: a low cost BIST technique for VLSI circuits. IEEE Trans. 1989, CAD, Vol. CAD-8, No. 1, pp.46–55.Google Scholar
  24. [24]
    M. Chatterjee, D.K. Pradhan. A novel pattern generator for near-perfect fault coverage. VLSI Test Symposium, 1995, pp.417–425.Google Scholar
  25. [25]
    G. Jervan, H. Kruus, Z. Peng, R. Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. Proc. ISQED, San Jose, March 18–20, 2002, pp.273–279.Google Scholar
  26. [26]
    R. Kraus, O. Kowarik, K. Hoffmann, D. Oberle, “Design for Test of Mbit RAMs”, Proc. Of the International Test Conference, Aug. 1989, pp. 316–321.Google Scholar
  27. [27]
    M.L. Bushnell, V.D. Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p.Google Scholar
  28. [28]
    M. Nicolaidis, “An Efficient Built-in Self-Test Scheme for Functional Test of Embedded RAMs”, Proc. Of the IEEE Fault Tolerant Computer Systems Conf., 1985, pp. 118–123.Google Scholar
  29. [30]
    W. J. Dally, B. Towles, “Route packets, not wires: On-chip interconnection networks”, Proceedings of the 38th Design Automation Conference, June 2001.Google Scholar
  30. [31]
    M. Renovell, J.M. Portal, J. Figueras, Y. Zorian, “Testing the Interconnect of RAM-based FPGAs”, IEEE Design & Test, January-March 1998, pp. 45–50.Google Scholar
  31. [32]
    W.H. Kautz, “Testing for Faults in Wiring Networks”, IEEE Trans. Computers, Vol. C-23, No. 4, 1974, pp. 358–363.Google Scholar

Copyright information

© Kluwer Academic Publishers 2003

Authors and Affiliations

  • Raimund Ubar
    • 1
  • Jaan Raik
    • 1
  1. 1.Tallinn Technical UniversityEstonia

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