Testing Strategies for Networks on Chip

  • Raimund Ubar
  • Jaan Raik


The complexity of Networks-on-Chip (NoC) makes the application of traditional test methods obsolete. For NoC, a combination of methods known from the System-on-Chip, memory and FPGA test areas should be used. That includes functional test, scan test, logic BIST, RAM BIST and testing of interconnect switches and wires. The increasing complexities of systems based on deep-submicron technologies cause two contrary trends: low-level defect-orientation to reach the high reliability of testing and high-level behavioral modeling to reach the efficiency of test generation. Hierarchical approaches seem to be the solution. Built-in Self-Test (BIST) is the main concept for testing the cores in systems on chip. Hybrid BIST containing both hardware and software components is probably the most promising approach to test the nodes of NoC. In densely packaged NoC with embedded memories and reusable cores scan-based approaches, P1500 standard for core test, test access mechanisms, test control and isolation issues are prospective methods. Testing the NoC interconnect switches and wires is also an important issue.


Test Pattern Fault Coverage Linear Feedback Shift Register Test Pattern Generation March Test 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 2003

Authors and Affiliations

  • Raimund Ubar
    • 1
  • Jaan Raik
    • 1
  1. 1.Tallinn Technical UniversityEstonia

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