This chapter described the usage and operation of the Physical Compiler. With the introduction of this capability, Synopsys has solved the long- standing problem of discrepancy between the delays estimated by the wire- load models and the final resulting routed design.
Different flows and techniques were described along with helpful scripts to guide the user in performing successful synthesis, placement and scan chain ordering.
Few problems associated with PhyC were also discussed. Although in time these problem will most certainly be corrected. Still it is the intent of this chapter to make readers aware of these issues in case they are using this version of PhyC.
Several new add-ons to Physical Compiler have recently been announced (the Clock Tree Compiler and the Route Compiler) that will enhance the capability of this tool enormously. These add-ons have been mentioned in this Chapter, however the usage and operation have not been described due to the unavailability of these options at the time of writing this book.
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