Advertisement

Oversampling A/D Converters

  • Mikael Gustavsson
  • J. Jacob Wikner
  • Nianxiong Nick Tan
Chapter
Part of the The International Series in Engineering and Computer Science book series (SECS, volume 543)

Summary

In this chapter we have discussed oversampling sigma-delta converters. They are suitable for high resolutions but the high oversampling ratio (OSR) limits the signal bandwidth. To increase the signal bandwidth cascaded modulators have been discussed. Gain errors in the integrators cause leakage of low order quantization noise at the output which limits the resolution of the converter. The integrator gain errors need not be as accurate as the full resolution and converters with up to 15 – 16 bit have been successfully implemented without calibration. To further reduce the quantization noise in the modulator a multi-bit quantizer can be used in the last stage of the converter. For a single stage modulator a multi-bit quantizer would require calibration since the DAC linearity directly limits linearity of the OSADC. For cascaded modulator however, the signal in the last stage has a weak correlation to the input signal and linearity errors in the multi-bit DAC will cause noise, not distortion. In addition to this the DAC linearity error is noise shaped, which significantly reduces the required linearity of the DAC. We have also discussed SC implementations of oversampled sigma-delta converters and investigated some of the most important limitations and how they affect the performance of the modulator. Based on the discussions and design example was presented.

Keywords

Quantization Noise Slew Rate Signal Bandwidth Gain Error Parasitic Capacitor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Conveners: Theory, Design and Simulation, IEEE Press, 1997.Google Scholar
  2. [2]
    G. Yin and W. Sansen, “A High-Frequency and High-Resolution Fourth-Order ΣΔA/D Converter in BiCMOS Technology”, 1EEE J. of Solid-State Circuits, vol. 29, no. 8, pp. 857–865, Aug. 1994.CrossRefGoogle Scholar
  3. [3]
    M. Sarhang-Nejad and G. C. Temes, “A High-Resolution Multibit ΣΔ ADC with Digital Correction and Relaxed Amplifier Requirements”, IEEE J. of Solid-State Circuits, vol. 28, no. 6, pp. 648–660, June 1993.CrossRefGoogle Scholar
  4. [4]
    Y. Geerts, A. M. Merques, M. Steyaert and W. Sansen “A 3.3-V, 15-bit, Delta-Sigma ADC with a Signal bandwidth of 1.1 MHz for ADSL Applications”, IEEE J. of Solid-State Circuits, vol. 34, no. 7, pp. 927–36, July 1999.CrossRefGoogle Scholar
  5. [5]
    H. Baher and E. Afifi, “Novel Fourth-Order Sigma-Delta Converter”, Electronics Letters, vol. 28, no. 15, pp. 1437–38, 16th July 1992.CrossRefGoogle Scholar
  6. [6]
    R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems, Springer-Verlag Berlin Heidelberg, 1989.CrossRefGoogle Scholar
  7. [7]
    G. Yin, F. Stubbe and W. Sansen, “A 16-b 320-kHz CMOS A/D Converter Using Two-Stage Third-Order ΣΔ Noise Shaping”, IEEE J. of Solid-State Circuits, vol. 28, no. 6, pp. 640–7, June 1993.CrossRefGoogle Scholar
  8. [8]
    P. J. Hurst and W. J. McIntyre, “Double Sampling in Switched-Capacitor Delta-Sigma A/D Converters”, Intl. Symp. on Circuits and Systems, ISCAS’90, pp. 902–905, 1990.Google Scholar
  9. [9]
    L. Yu and M. Snelgrove, “Mismatch Cancellation for Double-sampling Sigma-Delta Modulators”, Intl. Symp. on Circuits and Systems, ISCAS’98, pp. 356–9, 1998.Google Scholar
  10. [10]
    D. Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri and C. Dallavalle, “Low-Voltage Double-Sampled ΣΔ Converters”, IEEE J. of Solid-State Circuits, vol. 32, no. 12, pp. 1907–1919, Dec. 1997.CrossRefGoogle Scholar
  11. [11]
    L. A. Williams, III, and B. Wooley, “A Third-Order Sigma-Delta Modulator with Extended Dynamic Range”, IEEE J. of Solid-State Circuits, vol. 29, no. 3, pp. 193–202, Match 1994.CrossRefGoogle Scholar
  12. [12]
    R. Naiknaware and T. Fiez, “Power Optimization of ΣΔ Analog-to-Digital Converters Based on Slewing and Partial Settling Considerations”, Intl. Symp. on Circuits and Systems, ISCAS’98Google Scholar

Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Mikael Gustavsson
  • J. Jacob Wikner
  • Nianxiong Nick Tan

There are no affiliations available

Personalised recommendations