Oversampling A/D Converters
In this chapter we have discussed oversampling sigma-delta converters. They are suitable for high resolutions but the high oversampling ratio (OSR) limits the signal bandwidth. To increase the signal bandwidth cascaded modulators have been discussed. Gain errors in the integrators cause leakage of low order quantization noise at the output which limits the resolution of the converter. The integrator gain errors need not be as accurate as the full resolution and converters with up to 15 – 16 bit have been successfully implemented without calibration. To further reduce the quantization noise in the modulator a multi-bit quantizer can be used in the last stage of the converter. For a single stage modulator a multi-bit quantizer would require calibration since the DAC linearity directly limits linearity of the OSADC. For cascaded modulator however, the signal in the last stage has a weak correlation to the input signal and linearity errors in the multi-bit DAC will cause noise, not distortion. In addition to this the DAC linearity error is noise shaped, which significantly reduces the required linearity of the DAC. We have also discussed SC implementations of oversampled sigma-delta converters and investigated some of the most important limitations and how they affect the performance of the modulator. Based on the discussions and design example was presented.
KeywordsQuantization Noise Slew Rate Signal Bandwidth Gain Error Parasitic Capacitor
Unable to display preview. Download preview PDF.
- S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Conveners: Theory, Design and Simulation, IEEE Press, 1997.Google Scholar
- P. J. Hurst and W. J. McIntyre, “Double Sampling in Switched-Capacitor Delta-Sigma A/D Converters”, Intl. Symp. on Circuits and Systems, ISCAS’90, pp. 902–905, 1990.Google Scholar
- L. Yu and M. Snelgrove, “Mismatch Cancellation for Double-sampling Sigma-Delta Modulators”, Intl. Symp. on Circuits and Systems, ISCAS’98, pp. 356–9, 1998.Google Scholar
- R. Naiknaware and T. Fiez, “Power Optimization of ΣΔ Analog-to-Digital Converters Based on Slewing and Partial Settling Considerations”, Intl. Symp. on Circuits and Systems, ISCAS’98Google Scholar