Advertisement

Time-Interleaved A/D Converters

  • Mikael Gustavsson
  • J. Jacob Wikner
  • Nianxiong Nick Tan
Chapter
Part of the The International Series in Engineering and Computer Science book series (SECS, volume 543)

Summary

In this chapter we have discussed the time-interleaved ADC. The performance is limited by mismatches between the channels. Gain and offset errors can be calibrated. A more severe problem is the phase skew errors which increases at high signal frequencies. The most effective way to reduce these errors is to use an input S/H circuit which usually needs an opamp that runs at the full speed of the ADC. The opamp is therefore difficult to design and power consuming. An improved global passive sampling technique that does not need an opamp was introduced. The limitations of the technique was also discussed. The phase skew distortion can be reduced by 10 to 20 dB compared to not using a global sampling technique.

Keywords

Passive Sampling Parasitic Capacitance Sampling Instant Clock Phase Gain Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    W. C. Black and D. A. Hodghes, “Time Interleaved Converter Arrays” IEEE J. of Solid-State Circuits, vol. SC-15, no. 6, pp. 1022–29, Dec. 1980.CrossRefGoogle Scholar
  2. [2]
    K. Nagaraj, J. Fetterman, J. Anidjar, S. Lewis and R. G. Renninger, “A 250-mW, 8-b, 52-Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers” IEEE J. of Solid-Stale Circuits, vol. 32, no. 3, p.312–20, March 1997.CrossRefGoogle Scholar
  3. [3]
    Y. C. Jenq, “Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High-Speed Waveform Digitizers” IEEE Trans. on Instrumentation and Measurement, vol. 37, no. 2, pp. 245–51, June 1988.CrossRefGoogle Scholar
  4. [4]
    A. Petraglia and S. K. Mitra, “Analysis of Mismatch Effects Among A/D Converters in a Time-Interleaved Waveform Digitizer” IEEE Trans. on Instrumentation and Measurement, vol. 40, no. 5, pp. 831–5, Oct. 1991.CrossRefGoogle Scholar
  5. [5]
    J. B. Simoes, J. Landeck and C. M. B. A. Correia, “Nonlinearity of a Data-Acquisition System with Interleaving/Multiplexing” IEEE Trans. Instrumentation and Measurement, vol. 46, no. 6, pp. 1274–79, Dec. 1997.CrossRefGoogle Scholar
  6. [6]
    K. Y. Kim, N. Kusayanagi and A. A. Abidi, “A 10-b, 100-MS/s CMOS A/D Converter” IEEE J. of Solid-State Circuits, vol. 32, no. 6, pp. 302–11, Dec. 1997.Google Scholar
  7. [7]
    K. Poulton., J. J. Corcoran and T. Hornak, “A 1-GHz 6-bit ADC System”. IEEE J. of Solid-State Circuits, vol. SC-22, no. 6, pp. 962–70, Dec. 1987.CrossRefGoogle Scholar
  8. [8]
    K. Nakamura, M. Hotta, L. R. Carley and D. J. Allstot, “An 85 mW, 10 b, 40 Msample/s CMOS Parallel-Pipelined ADC” IEEE J. of Solid-State Circuits, vol. 30, no. 6, pp. 173–83, Dec. 1995.CrossRefGoogle Scholar
  9. [9]
    H. Jin, E. Lee and M. Hassoun, “Time-Interleaved A/D Converter with Channel Randomization”, IEEE Intern. Symp. on Circuits and Systems, ISCAS-97, vol. 1, pp. 425–8, 1997.Google Scholar
  10. [10]
    A. N. Karanicolas, H. S. Lee and K. L. Bacrania, “A 15-b 1 Msample/s Digitally Self-Calibrated Pipeline ADC” IEEE J. of Solid-State Circuits, vol. 28, no. 12, pp. 1207–15, Dec. 1993.CrossRefGoogle Scholar
  11. [11]
    E. G. Soenen and R. L. Geiger, “An Architecture and an Algorithm for Fully Digital Correction of Monolithic Pipelined ADC’s” IEEE Trans. on Circuits and Systems-II, vol. 42, no. 3, pp. 143–53, March 1995.CrossRefGoogle Scholar
  12. [12]
    T. H. Shu, B. S. Song and K. Bacrania, “A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter” IEEEJ. of Solid-State Circuits, vol. 30, no. 4, p. 443–52, April 1995.CrossRefGoogle Scholar
  13. [13]
    U. K. Moon, B. S. Song, “Background Digital Calibration Techniques for Pipelined ADCs” IEEE Trans. on Circuits and Systems-II, Vol. 44, No. 2, pp. 102–9, February 1997.CrossRefGoogle Scholar
  14. [14]
    K. Dyer, D. Fu, P. Hurst and S. Lewis, “A Comparison of Monolithic Background Calibration in Two Time-Interleaved Analog-to-Digital Converters” IEEE 1998 Intern. Symp. on Circuits and Systems, lSCAS-98, vol 1. pp. 13–16, 1998.Google Scholar
  15. [15]
    Y. C. Jenq, “Digital Spectra of Nonuniformly Sampled Signals: A Robust Sampling Time Offset Estimation Algorith for Ultra High-Speed Waveform Digitizers Using Interleaving” IEEE Trans. on Instrumentation and Measurement, vol. 39, no. 1, pp. 71–75, Feb. 1990.CrossRefGoogle Scholar
  16. [16]
    A. Petraglia and S. K. Mitra, “High-Speed A/D Conversion Incorporating a QMF Bank” IEEE Trans. on Instrumentation and Measurement, vol. 41, no. 3, pp. 427–31, June 1992.CrossRefGoogle Scholar
  17. [17]
    S. R. Velazques, Hybrid Filter Banks for Analig/Digital Conversion, Ph.D. Thesis at Massachusetts Institute of Technology, June 1997.Google Scholar
  18. [18]
    R. Khoini-Poorfard, L. B. Lim and D. A. Johns, “Time-Interleaved Oversampling A/D Converters: Theory and Practice” IEEE Trans. on Circuits and Systems-II, vol. 44, no. 8, pp. 634–45, Aug. 1997.CrossRefGoogle Scholar
  19. [19]
    S. K. Kong and W. H. Ku, “Effects of Non-Ideal Hadamard Modulators on the Performance of PDS ADC” Electronics Letters, vol. 33, no. 2, p. 109–10, 16th Jan. 1997.CrossRefGoogle Scholar
  20. [20]
    T. C. Choi and R. W. Brodersen, “Considerations for High-Frequnency Switched-Capacitor Ladder Filters” IEEE Trans. on Circuits and Systems., vol. cas-27, no. 6, pp. 545–52, June 1980.CrossRefGoogle Scholar

Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Mikael Gustavsson
  • J. Jacob Wikner
  • Nianxiong Nick Tan

There are no affiliations available

Personalised recommendations