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3D IC Heterogeneous Integration by FOWLP

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Fan-Out Wafer-Level Packaging

Abstract

Two 3D IC heterogeneous integrations by Fan-Out Wafer-Level Packaging (FOWLP) technology are presented in this chapter. The emphasis of the first such method is on the design, and of the other method, the emphasis is on the manufacturing process. The heterogeneous integration versus SoC (system-on-chip) will be briefly discussed. Some examples on the TSV (Through-Silicon Via)-less heterogeneous integration by FOWLP will also be presented. Since MCM (Multichip Module) is the frontier of heterogeneous integration and thus it will be briefly mentioned first.

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Authors and Affiliations

  1. ASM Pacific Technology, Hong Kong, New Territories, Hong Kong

    John H. Lau

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  1. John H. Lau
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Correspondence to John H. Lau .

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Lau, J.H. (2018). 3D IC Heterogeneous Integration by FOWLP. In: Fan-Out Wafer-Level Packaging. Springer, Singapore. https://doi.org/10.1007/978-981-10-8884-1_11

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  • DOI: https://doi.org/10.1007/978-981-10-8884-1_11

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-8883-4

  • Online ISBN: 978-981-10-8884-1

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