Abstract
Orthogonal Latin square (OLS) codes are one type of one-step majority logic decodable (OS-MLD) error correcting code. These codes provide fast and simple decoding procedure. The OLS codes are used for correcting multiple cell upsets (MCU) which occur in semiconductor memories due to radiation-induced soft errors. OLS codes are derived from Latin squares and can be efficiently implemented on reconfigurable architectures like field programmable gate arrays (FPGA). This paper describes the construction of OLS codes from their parity check matrices and the method for increasing the data block size by extending the original OLS code. Here, double error correcting OLS (32, 16) code and OLS (36, 20) code have been designed and implemented on SRAM-based Xilinx FPGA. The synthesis results of area and delay of the encoder and decoder blocks are also presented. It is observed that extending the OLS codes will result in significant overhead in terms of the overall available resources and the delay of the codec circuits.
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References
R.C. Baumann, Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans. Device Mater. Reliab. 5(3), 301–316 (2005)
B. Cooke, R. Muller, Error correcting codes. MIT Undergrad. J. Math. 1, 21–26 (1999)
M.Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes. IBM J. Res. Dev. 14, 395–401 (1970)
A. Dutta, N.A. Touba, Multiple bit upset tolerant memory using a selective cycle avoidance based SEC DED-DAEC code, in Proceedings of IEEE VLSI Test Symposium (2007), p. 349–354
S. Baeg, S. Wen, R. Wong, SRAM interleaving distance selection with a soft error failure model. IEEE Trans. Nucl. Sci. 56(4), 2111–2118 (2009)
S. Baeg, S. Wen, R. Wong, SRAM interleaving distance selection with a soft error failure model. IEEE Trans. Nucl. Sci. 56(4 (part 2)), 2111–2118 (2009)
S. Baeg, S. Wen, R. Wong, Minimizing soft errors in TCAM devices: a probabilistic approach to determining scrubbing intervals. IEEE Trans. Circuits Syst. I 57(4), 814–822 (2010)
T. Calin, M. Nicoladis, R. Velazco, Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nucl. Sci. 43(6), 2874–2878 (1996)
S.M. Jahinuzzaman, D.J. Rennie, M. Sachdev, A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE Trans. Nucl. Sci. 56(6), 3768–3773 (2009)
R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, Design of robust SRAM cells against single event multiple effects for nanometer technologies. IEEE Trans. Device Mater. Reliab. 15(3), 429–436 (2015)
P. Ankolekar, S. Rosner, R. Isaac, J. Bredow, Multi-bit error correction methods for latency-constrained flash memory systems. IEEE Trans. Device Mater. Reliab. 10(1), 33–39 (2010)
G. Neuberger, D. Kastensmidt, R. Reis, An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories. IEEE Des. Test Comput. 22(1), 50–58 (2005)
G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, Fault tolerant solid state mass memory for space applications. IEEE Trans. Aerosp. Electron. Syst. 41(4), 1353–1372 (2005)
S. Lin, D.J. Costello, Error Control Coding, 2nd edn. (Prentice-Hall, Englewood Cliffs, NJ, USA, 2004)
M.Y. Hsiao, D.C. Bossen, R.T. Chien, Orthogonal Latin square codes. IBM J. Res. Develop. 14(4), 390–394 (1970)
P. Reviriego, S. Pontarelli, A. Sánchez-Macián, J.A. Maestro, A method to extend orthogonal Latin square codes. IEEE Trans. Very Large Scale Integr. Syst. 22(7), 1635–1639 (2014)
P. Reviriego, S. Liu, A. Sánchez-Macián, L. Xiao, J. Maestro, A scheme to reduce the number of parity check bits in orthogonal Latin square codes. IEEE Trans. on Reliab. 66(2)
M. Demirci, P. Reviriego, J. Maestro, Implementing double error correction orthogonal Latin squares codes in SRAM-based FPGAs. Microelectron. Reliab. 56, 221–227 (2016)
J. Dénes, A.D. Keedwell, Latin Squares and Their Applications (Academic, San Francisco, CA, USA, 1974)
H.B. Mann, Analysis and Design of Experiments (Dover Publications, New York, 1949)
S. Hauck, A. De Hon Morgan, Reconfigurable Computing: The Theory and Practice of FPGA-based Computation (Kaufmann Publishers, Indian Reprint Edition, 2011)
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Sarkar, A., Samanta, J., Barman, A., Bhaumik, J. (2017). FPGA Implementation of OLS (32, 16) Code and OLS (36, 20) Code. In: Bhaumik, J., Chakrabarti, I., De, B.P., Bag, B., Mukherjee, S. (eds) Communication, Devices, and Computing. ICCDC 2017. Lecture Notes in Electrical Engineering, vol 470. Springer, Singapore. https://doi.org/10.1007/978-981-10-8585-7_14
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DOI: https://doi.org/10.1007/978-981-10-8585-7_14
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