Abstract
The particular form of the task graph of many telecommunication applications permits a high level of coarse grained parallelism. We consider a classification application on a telecommunication oriented multiprocessor system-on-chip (MP-SoC) platform. The hardware architecture hosting this type of application contains many programmable processors and dedicated hardware coprocessors, sharing the same address space. Inter-task communications are implemented via Multi-Writer Multi-Reader (MWMR) channels placed in shared-memory. To meet the strict requirements of this type of application, several performance bottlenecks have to be overcome. We show how our tool DSX (Design Space Explorer) helps to analyze these bottlenecks and outline the perspectives for further improvement.
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Notes
- 1.
Meanwhile, instruction set simulators for ARM7 and PowerPC 405 have been added [18], others are in preparation.
- 2.
Means of inter-task communication currently provided are MWMR channels, shared memory, mutex and synchronization barriers.
- 3.
The issue is the same between hardware and software tasks; the bursts size issuing from a hardware coprocessor can be configured at its creation.
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Genius, D., Faure, E., Pouillon, N. (2011). Mapping a Telecommunication Application on a Multiprocessor System-on-Chip. In: Gogniat, G., Milojevic, D., Morawiec, A., Erdogan, A. (eds) Algorithm-Architecture Matching for Signal and Image Processing. Lecture Notes in Electrical Engineering, vol 73. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9965-5_3
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