Minimizing Jitter in Ethernet Using a Linear Backoff for Real-Time Robot Control Communication and Its Implementation on FPGA

Abstract

Deterministic control communication is a backbone of many novel robotic complex systems, e.g HUBO uses CAN. The aim of this paper, in contrast, is to develop an approach for cheap and deterministic control communication using Ethernet real-time control communication. A half-duplex Ethernet network populated with a small/medium number of Media Access Controllers (MACs) is used for timed real-time communication. Matlab and Field-programmable gate array (FPGA) technology, i.e Xilinx XC3S500E from the Spartan-3E family, are used to simulate and implement the Ethernet communication strategy. The FPGA units are programmed in Verilog using Xilinx ISE 11.1 software tools. For communication, a time-triggered approach is used, i.e a synchronization signal triggers the sending of data from each Ethernet data transmitting unit. Moreover, data packages are sent at well defined times after each trigger instant to reduce collisions. Collisions mainly occur due to jitter of the transmitter system, so that arbitration (similar to CANopen) is necessary. A Linear Backoff scheme is used in comparison to the Binary Exponential backoff scheme. This paper analyzes and investigates how the backoff scheme affects the performance of the Carrier Sense Multiple Access protocol with Collision Detection (CSMA/CD) in a basic MAC, in terms of data arrival characteristics, i.e jitter and delay for deterministic control communication. We propose to assign different minimal back-off times for each of the CSMA/CD controller units and FPGA boards to minimize packet collisions.