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International Static Analysis Symposium

SAS 2011: Static Analysis pp 146–162Cite as

Verifying Fence Elimination Optimisations

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6887))

Abstract

We consider simple compiler optimisations for removing redundant memory fences in programs running on top of the x86-TSO relaxed memory model. While the optimisations are performed using standard thread-local control flow analyses, their correctness is subtle and relies on a non-standard global simulation argument. The implementation and the proof of correctness are programmed in Coq as part of CompCertTSO, a fully-fledged certified compiler from a concurrent extension of a C-like language to x86 assembler. In this article, we describe the soundness proof of the optimisations and evaluate their effectiveness.

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Author information

Authors and Affiliations

  1. MPI-SWS, Germany

    Viktor Vafeiadis

  2. INRIA, France

    Francesco Zappa Nardelli

Authors
  1. Viktor Vafeiadis
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  2. Francesco Zappa Nardelli
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Editor information

Editors and Affiliations

  1. Computer Science Deptartement, Technion, 32000, Technion City, Haifa, Israel

    Eran Yahav

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Vafeiadis, V., Zappa Nardelli, F. (2011). Verifying Fence Elimination Optimisations. In: Yahav, E. (eds) Static Analysis. SAS 2011. Lecture Notes in Computer Science, vol 6887. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23702-7_14

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  • DOI: https://doi.org/10.1007/978-3-642-23702-7_14

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-23701-0

  • Online ISBN: 978-3-642-23702-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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