Abstract
Dual Rail Precharge circuits offer an effective way to address Differential Power Analysis Attacks, provided routing of differential signals is fully balanced. Fat Wire [1] and Backend Duplication [2] methods address this problem. However they do not consider the effect of coupling capacitance on adjacent differential signals. In this paper we propose a new method, Divided Backend Duplication, which is based on Divided Wave Dynamic Differential Logic [3] and Backend Duplication [2], that effectively addresses balanced routing problem of Dual Rail Precharge circuits. Experimental results on an AES test circuit in 130nm technology show improvements in achieving a balanced dual rail design. Further our method can also be successfully applied to FPGAs. Results from an sbox test circuit implementation on a Xilinx FPGA are presented.
Chapter PDF
Similar content being viewed by others
References
Tiri, K., Verbauwhede, I.: Place and Route for Secure Standard Cell Design. In: 6th International Conference on Smart Card Research and Advanced Applications (CARDIS 2004), August 2004, pp. 143–158 (2004)
Guilley, S., Hoogvorst, P., Mathieu, Y., Pacalet, R.: The Backend Duplication Method. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 383–397. Springer, Heidelberg (2005)
Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: DATE 2004: Proceedings of the conference on Design, automation and test in Europe, pp. 246–251. IEEE Computer Society, Washington (2004)
Ravi, S., Raghunathan, A., Kocher, P., Hattangady, S.: Security in embedded systems: Design challenges. Trans. on Embedded Computing Sys. 3(3), 461–491 (2004)
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M.J. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Bucci, M., Guglielmo, M., Luzzi, R., Trifiletti, A.: A power consumption randomization countermeasure for DPA-resistant cryptographic processors. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol. 3254, pp. 481–490. Springer, Heidelberg (2004)
Sokolov, D., Murphy, J., Bystrov, A., Yakovlev, A.: Design and Analysis of Dual-Rail Circuits for Security Applications. IEEE Transactions on Computers 54(4), 449–460 (2005)
Tiri, K., Verbauwhede, I.: Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 125–136. Springer, Heidelberg (2003)
Baddam, K., Zwolinski, M.: Path switching: a technique to tolerate dual rail routing imbalances. Design Automation for Embedded Systems (accepted for publication) (2008), http://www.springerlink.com/content/32181g28411w2121 , doi:10.1007/s10617-008-9017-z
Pramstaller, N., Oswald, E., Mangard, S., Gürkaynak, F.K., Haene, S.: A Masked AES ASIC Implementation. In: Ofner, E., Ley, M. (eds.) Proceedings of Austrochip 2004, Villach, Austria, October 2004, pp. 77–82 (2004)
Popp, T., Mangard, S.: Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172–186. Springer, Heidelberg (2005)
Tiri, K., Verbauwhede, I.: Prototype IC with WDDL and Differential Routing DPA Resistance Assessment. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 354–365. Springer, Heidelberg (2005)
Bucci, M., Giancane, L., Luzzi, R., Trifiletti, A.: Three-Phase Dual-Rail Pre-charge Logic. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 232–241. Springer, Heidelberg (2006)
Yu, P., Schaumont, P.: Secure FPGA circuits using controlled placement and routing. In: CODES+ISSS 2007: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pp. 45–50. ACM, New York (2007)
Bouesse, G.F., Renaudin, M., Dumont, S., Germain, F.: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. In: DATE 2005: Proceedings of the conference on Design, Automation and Test in Europe, pp. 424–429. IEEE Computer Society, Washington (2005)
Weste, N., Harris, D.: CMOS VLSI Design A Circuits and Systems Perspective, 3rd edn. Addison-Wesley, Reading (2004)
Si2.org: OpenAccess Coalition (April 2007), http://openeda.si2.org/
Cadence Design Systems: ENCOUNTER DIGITAL IC DESIGN PLATFORM (April 2007), http://www.cadence.com/products/digital_ic/index.aspx?lid=dic
Tiri, K., Verbauwhede, I.: Synthesis of Secure FPGA Implementations. In: International Workshop on Logic and Synthesis (IWLS 2004), June 2004, pp. 224–231 (2004)
Xilinx Inc: Xilinx Inc. (April 2007), http://www.xilinx.com/
Gandolfi, K., Mourtel, C., Olivier, F.: Electromagnetic Analysis: Concrete Results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Baddam, K., Zwolinski, M. (2008). Divided Backend Duplication Methodology for Balanced Dual Rail Routing. In: Oswald, E., Rohatgi, P. (eds) Cryptographic Hardware and Embedded Systems – CHES 2008. CHES 2008. Lecture Notes in Computer Science, vol 5154. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85053-3_25
Download citation
DOI: https://doi.org/10.1007/978-3-540-85053-3_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-85052-6
Online ISBN: 978-3-540-85053-3
eBook Packages: Computer ScienceComputer Science (R0)