Abstract
Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.
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References
Chandrakasan, A., Bowhill, W.J., Fox, F.: Design of high-performance microprocessor circuits. Wiley, New York (2001)
Gneiting, T., Jalowiecki, I.P.: Influence of process parameter variations on the signal distribution behavior of wafer scale integration devices. IEEE Trans. Components, Packaging and Manufacturing Technology Part B 18(3), 424–430 (1995)
Chang, H., Qian, H., Sapatnekar, S.S.: The certainty of uncertainty: randomness in nanometer design. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol. 3254, pp. 36–47. Springer, Heidelberg (2004)
Nassif, S.: Design for variability in DSM technologies. In: IEEE Int. Symp. Quality Electronic design, pp. 451–454. IEEE Computer Society Press, Los Alamitos (2000)
Nardi, A., Neviani, A., Zanoni, E., Quarantelli, M., Guardiani, C.: Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies. IEEE Trans. Semiconductor Manufacturing 12(4), 396–402 (1999)
Singhal, K., Visvanathan, V.: Statistical device models from worst case files and electrical test data. IEEE Trans. Semiconductor Manufacturing 12(4), 470–484 (1999)
Mutlu, A.A., Kwong, C., Mukherjee, A., Rahman, M.: Statistical circuit performance variability minimization under manufacturing variations. In: ISCAS 06 IEEE Int. Symp. on Circuits and Systems, pp. 3025–3028. IEEE Computer Society Press, Los Alamitos (2006)
Jyu, H.-F., Malik, S., Devadas, S., Keutzer, K.W.: Statistical timing analysis of combinatorial logic circuits. IEEE Trans. VLSI Systems 1(2), 126–137 (1993)
Chang, H., Sapatnekar, S.S.: Statistical timing analysis under spatial correlations. IEEE Trans. on CAD 24(9), 1467–1482 (2005)
Jess, J.A.G., Kalafala, K., Naidu, S.R., Otten, R.H.J.M., Visweswariah, C.: Statistical timing for parametric yield prediction of digital integrated circuits. IEEE Trans. on CAD 25(11), 2376–2392 (2006)
Agarwal, A., Mukhopadhyay, S., Raychowdhury, A., Roy, K., Kim, C.H.: Leakage power analysis and reduction for nanoscale circuits. IEEE Micro 26(2), 68–80 (2006)
Rao, R., Srivastava, A., Blaauw, D., Sylvester, D.: Statistical estimation of leakage current considering inter- and intra-die process variation. In: ISLPED 2003 Int. Symp. Low-Power Electronics and Design, pp. 84–89 (2003)
Chang, H., Sapatnekar, S.S.: Full-chip analysis of leakage power under process variations, including spatial correlations. In: DAC 2005 Proc. Design Automation Conf., pp. 523–528 (2005)
Chen, T., Naffziger, S.: Comparison of Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) for improving delay and leakage under the presence of process variation. IEEE Trans. VLSI Systems 11(5), 888–899 (2005)
ITRS: The International Technology Roadmap for Semiconductors, 2005 edn. (2005)
Verilog-A language reference manual, Version 1.0. Open Verilog International (1996)
Ashenden, P.J., Peterson, G.D., Teegarden, D.A.: The system designer’s guide to VHDL-AMS. Morgan Kaufmann, San Francisco (2002)
Auvergne, A., Daga, J.M., Rezzoug, M.: Signal transition time effect on CMOS delay evaluation. IEEE Trans. Circuits and Systems I 47(9), 1362–1369 (2000)
Bowman, K.A., Duvall, S.G., Meindl, J.D.: Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid-State Circuits 37(2), 183–190 (2002)
Bowman, K.A., Austin, B.L., Eble, J.C., Tang, X., Meindl, J.D.: A physical alpha-power law MOSFET model. J. Solid-State Circuits 34(10), 1410–1414 (1999)
Gu, R.X., Elmasry, M.I.: Power dissipation analysis and optimization of deep submicron CMOS digital circuits. IEEE J. Solid-State Circuits 31(5), 707–713 (1996)
Rao, R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: DAC 2004 Proc. Design Automation Conf., pp. 442–447 (2004)
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Centurelli, F., Giancane, L., Olivieri, M., Scotti, G., Trifiletti, A. (2007). A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_50
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DOI: https://doi.org/10.1007/978-3-540-74442-9_50
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