Abstract
Software verification technology has the potential to improve the quality of software. The basic technique is to generate verification conditions for a given program and to discharge these proof obligations using a theorem prover. Encoding the verification conditions is a delicate process, not just because it must capture the intended programming semantics, but also because it must yield formulas that a theorem prover can process effectively.
In this talk, I will discuss the process of generating verification conditions in the program verifier for the object-oriented language Spec#. I will highlight design decisions we have made in modeling programs and targeting SMT solvers, lessons we have learned, and challenges that remain ahead.
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© 2007 Springer-Verlag Berlin Heidelberg
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Leino, K.R.M. (2007). Designing Verification Conditions for Software. In: Pfenning, F. (eds) Automated Deduction – CADE-21. CADE 2007. Lecture Notes in Computer Science(), vol 4603. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73595-3_23
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DOI: https://doi.org/10.1007/978-3-540-73595-3_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73594-6
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