Abstract
The design of High Performance Computing (HPC) relies to a large extent on simulations to optimize components of such complex systems. A key hardware component of the interconnection network in HPC environments is the Network Interface Card (NIC). In spite of the popularity of simulation-based approaches in the computer architecture domain, few authors have focused on simulators design methodologies. In this paper, we describe the stages of implementing a simulation model to solve a real problem—modeling NIC buffer. We present a general methodology for helping users to build Hardware Description Language (HDL)/SystemC models targeted to fulfil features such as performance evaluation of compute nodes. The developed VHDL model allows reproducibility and can be used as a tool in the area of HPC education.
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It should be noted that in this work the terms ‘‘Ethernet frame’’, and ‘‘Ethernet packet’’, i.e., data units exchanged at the data-link level, are used interchangeably.
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Acknowledgments
This work is supported by the Ministry of Education and Science of Russian Federation under contract No02.G25.31.0061 12/02/2013 (Government Regulation No 218 from 09/04/2010).
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Garay, G.R., Tchernykh, A., Drozdov, A.Y., Novikov, S.V., Vladislavlev, V.E. (2016). A VHDL-Based Modeling of Network Interface Card Buffers: Design and Teaching Methodology. In: Gitler, I., Klapp, J. (eds) High Performance Computer Applications. ISUM 2015. Communications in Computer and Information Science, vol 595. Springer, Cham. https://doi.org/10.1007/978-3-319-32243-8_18
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DOI: https://doi.org/10.1007/978-3-319-32243-8_18
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