Abstract
In the presence of dynamic insertions and deletions into a partially reconfigurable FPGA, fragmentation is unavoidable. This poses the challenge of developing efficient approaches to dynamic defragmentation and reallocation. One key aspect is to develop efficient algorithms and data structures that exploit the two-dimensional geometry of a chip, instead of just one. We propose a new method for this task, based on the fractal structure of a quadtree, which allows dynamic segmentation of the chip area, along with dynamically adjusting the necessary communication infrastructure. We describe a number of algorithmic aspects, and present different solutions. We also provide experimental data for various scenarios, indicating practical usefulness of our approach.
This work was supported by the DFG Research Group FOR-1800, “Controlling Concurrent Change”, under contract number FE407/17-1.
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Fekete, S.P., Reinhardt, JM., Scheffer, C. (2016). An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration. In: Hannig, F., Cardoso, J.M.P., Pionteck, T., Fey, D., Schröder-Preikschat, W., Teich, J. (eds) Architecture of Computing Systems – ARCS 2016. ARCS 2016. Lecture Notes in Computer Science(), vol 9637. Springer, Cham. https://doi.org/10.1007/978-3-319-30695-7_23
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DOI: https://doi.org/10.1007/978-3-319-30695-7_23
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