Abstract
As system on a chip (SoC) designs continue to head in the direction of miniaturization, with an ever increasing size of components, three-dimensional (3D) integration technologies are used to satisfy performance enhancements. With increasing number of cores, bus based SoC designs do not scale well, hence network on chip (NoC) architectures are introduced to avoid communication bottlenecks. Since two-dimensional NoC designs are not easy to partition across 3D chip layers, we introduce an adaptive 3D NoC architecture. The bandwidth and frequency of inter layer connections can be chosen independently from the router links within a layer. To prevent thermal hot spots in the middle of the chip, memory layers are placed in between compute layers. Supplemental this solves the high demand of our distributed memory architecture.
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Acknowledgment
This work was supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Center “Invasive Computing” (SFB/TR89).
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Friederich, S., Lehmann, N., Becker, J. (2016). Adaptive Bandwidth Router for 3D Network-on-Chips. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_30
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DOI: https://doi.org/10.1007/978-3-319-30481-6_30
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