Abstract
The trend towards more parallelism in information processing is unbroken. Manycore architectures provide both massive parallelism and flexibility, yet they raise the level of complexity in design and programming. Prototyping of such architectures helps in handling this complexity by evaluating the design space and discovering design errors. Several system simulators exist but they can only be used for early software development and interface specification. FPGA-based prototypes on the other hand are restricted by available FPGA resources or expensive multi-FPGA prototyping platforms. We present a hybrid prototyping approach for manycore systems that consists of an FPGA-part and a virtual part of the architecture on a host system. The hybrid prototyping requires less FPGA resources while retaining its speed advantage and enabling flexible modeling in the virtual platform.
We describe the concept, provide an analysis of timing accuracy and synchronization of the FPGA with the Virtual Platform (VP) and show an example in which the hybrid prototype is used for feature development and evaluation of a scientific manycore architecture. The hybrid prototype allows us to evaluate a 7 \(\times \) 7 architecture on a Virtex-7 XC7VX485T FPGA board which otherwise could only fit a reduced 2 \(\times \) 2 design of our architecture.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Open Virtual Platforms (OVP). http://www.ovpworld.org/
Synopsys Hybrid Prototyping Solution. https://www.synopsys.com/verification/virtual-prototyping/virtualizer/hybrid-prototyping.html
Binkert, N., et al.: The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1 (2011). https://doi.org/10.1145/2024716.2024718
Goossens, K., Bennebroek, M., Hur, J.Y., Wahlah, M.A.: Hardwired networks on chip in FPGAs to unify functional and configuration interconnects. In: Second ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2008. IEEE, April 2008. https://doi.org/10.1109/nocs.2008.4492724
Kamali, H.M., Hessabi, S.: AdapNoC: a fast and flexible FPGA-based NoC simulator. In: 2016 26th International Conference on Field Programmable Logic and Applications, FPL. IEEE, August 2016. https://doi.org/10.1109/fpl.2016.7577377
Kwon, Y.S., Kyung, C.M.: Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 24(9), 1444–1456 (2005). https://doi.org/10.1109/tcad.2005.852035
Lotlikar, S., Pai, V., Gratz, P.V.: AcENoCs: a configurable HW/SW platform for FPGA accelerated NoC emulation. In: 2011 24th International Conference on VLSI Design. IEEE, January 2011. https://doi.org/10.1109/vlsid.2011.46
Lyberis, S., et al.: Formic: cost-efficient and scalable prototyping of manycore architectures. In: 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines. IEEE, April 2012. https://doi.org/10.1109/fccm.2012.20
Masing, L., Srivatsa, A., KreB, F., Anantharajaiah, N., Herkersdorf, A., Becker, J.: In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures. In: 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, September 2018. https://doi.org/10.1109/mcsoc2018.2018.00033
Papamichael, M.K.: Fast scalable FPGA-based Network-on-Chip simulation models. In: Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMPCODE 2011. IEEE, July 2011. https://doi.org/10.1109/memcod.2011.5970513
Rodriguez-Andina, J., Moure, M., Valdes, M.: Features, design tools, and application domains of FPGAs. IEEE Trans. Ind. Electron. 54(4), 1810–1823 (2007). https://doi.org/10.1109/tie.2007.898279
Saboori, E., Abdi, S.: Hybrid prototyping of multicore embedded systems. In: 2013 IEEE Conference Publications on Design, Automation & Test in Europe Conference & Exhibition (DATE) (2013). https://doi.org/10.7873/date.2013.330
Schreiner, S., Gorgen, R., Gruttner, K., Nebel, W.: A quasi-cycle accurate timing model for binary translation based instruction set simulators. In: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS. IEEE, July 2016. https://doi.org/10.1109/samos.2016.7818371
Wang, D., Lo, C., Vasiljevic, J., Jerger, N.E., Steffan, J.G.: DART: a programmable architecture for NoC simulation on FPGAs. IEEE Trans. Comput. 63(3), 664–678 (2014). https://doi.org/10.1109/tc.2012.121
Acknowledgment
This work was supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Center Invasive Computing [SFB/TR 89].
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Masing, L., Lesniak, F., Becker, J. (2019). Hybrid Prototyping for Manycore Design and Validation. In: Hochberger, C., Nelson, B., Koch, A., Woods, R., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2019. Lecture Notes in Computer Science(), vol 11444. Springer, Cham. https://doi.org/10.1007/978-3-030-17227-5_23
Download citation
DOI: https://doi.org/10.1007/978-3-030-17227-5_23
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-17226-8
Online ISBN: 978-3-030-17227-5
eBook Packages: Computer ScienceComputer Science (R0)