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ASA-routing: A-Star Adaptive Routing Algorithm for Network-on-Chips

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Algorithms and Architectures for Parallel Processing (ICA3PP 2018)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 11335))

Abstract

Network congestion is not an uncommon occurrence even when a routing algorithm is well-designed, especially under the condition of a high injection rate. Moreover, it strongly affects the network’s overall performance as a result of increased packet latency. However, the majority of existing congestion avoidance methods either utilize local information or are incredibly complicated. The A-star algorithm is characterized as a heuristic algorithm typically used for the purpose of obtaining an optimal path. In this paper, we propose a novel route selection strategy for network-on-chips is proposed. This strategy is based on the A-star algorithm called ASA-routing. This selection method can be coupled with any deadlock-free adaptive routing algorithm. The ASA-routing utilizes routing table information in order to select as non-congested as possible of output channels for forwarding packets. The congestion information should be dynamically updated according to previously routed packets’ transmission latency. Based on experimental results for different traffic patterns and network loads, the manner in which our method can be applied to the repetitive turn model routing and the odd-even turn routing is outlined, improving both the average latency and the throughput.

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References

  1. International technology roadmap for semiconductors interconnect. Tech. rep., Semiconductor Industry Assoc. (2006)

    Google Scholar 

  2. Ascia, G., Catania, V., Palesi, M., Patti, D.: Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Trans. Comput. 57(6), 809–820 (2008)

    Article  MathSciNet  Google Scholar 

  3. Boura, Y.M., Das, C.R.: A class of partially adaptive routing algorithms for n\(\_\)dimensional meshes. In: Proceedings of the 1993 International Conference on Parallel Processing, pp. 175–182. CRC Press, NY (1993)

    Google Scholar 

  4. Chabini, I., Lan, S.: Adaptations of the a* algorithm for the computation of fastest paths in deterministic discrete-time dynamic networks. IEEE Trans. Intell. Transp. Syst. 3(1), 60–74 (2002)

    Article  Google Scholar 

  5. Chiu, G.: The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)

    Article  Google Scholar 

  6. Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Design Automation Conference, pp. 684–689. ACM, Las Vegas (2001)

    Google Scholar 

  7. Duato, J., Yalamanchili, S., Ni, L.M.: Interconnection Networks: An Engineering Approach. Morgan Kaufmann, San Francisco (2003)

    Google Scholar 

  8. Ebrahimi, M., Daneshtalab, M., Liljeberg, P., Plosila, J., Tenhunen, H.: CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks. In: Design, Automation & Test in Europe Conference & Exhibition, DATE, pp. 320–325. IEEE, Dresden (2012)

    Google Scholar 

  9. Farahnakian, F., Ebrahimi, M., Daneshtalab, M., Liljeberg, P., Plosila, J.: Q-learning based congestion-aware routing algorithm for on-chip network. In: Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, NESEA, pp. 1–7. IEEE Computer Society, Perth (2011)

    Google Scholar 

  10. Feng, W., Shin, K.G.: Impact of selection functions on routing algorithm performance in multicomputer networks. In: In: Proceedings of the 11th international conference on Supercomputing, pp. 132–139. ACM, Austria (1997)

    Google Scholar 

  11. Glass, C.J., Ni, L.M.: The turn model for adaptive routing. J. ACM 41(5), 874–902 (1994)

    Article  Google Scholar 

  12. Hart, P.E., Nilsson, N.J., Raphael, B.: A formal basis for the heuristic determination of minimum cost paths. IEEE Trans. Syst. Sci. Cybern. 4(2), 100–107 (1968)

    Article  Google Scholar 

  13. Hu, J., Marculescu, R.: Dyad: smart routing for networks-on-chip. In: Proceedings of the 41st Design Automation Conference, pp. 260–263. ACM, San Diego (2004)

    Google Scholar 

  14. Li, M., Zeng, Q., Jone, W.: Dyxy: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of the 43rd Design Automation Conference, pp. 849–852. ACM, San Francisco (2006)

    Google Scholar 

  15. Lotfi-Kamran, P., Daneshtalab, M., Lucas, C., Navabi, Z.: BARP-A dynamic routing protocol for balanced distribution of traffic in NoCs. In: Design. Automation and Test in Europe, DATE, pp. 1408–1413. ACM, Munich (2008)

    Google Scholar 

  16. Martínez, J.C., Silla, F., López, P., Duato, J.: On the influence of the selection function on the performance of networks of workstations. In: Third International Symposium High Performance Computing, ISHPC, pp. 292–299. Springer, Tokyo (2000)

    Google Scholar 

  17. Ni, L.M., McKinley, P.K.: A survey of wormhole routing techniques in direct networks. IEEE Comput. 26(2), 62–76 (1993)

    Article  Google Scholar 

  18. Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J., van Meerbergen, J.L., Wielage, P., Waterlander, E.: Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In: Design, Automation and Test in Europe Conference and Exposition (DATE), pp. 10350–10355. IEEE Computer Society, Munich (2003)

    Google Scholar 

  19. Schwiebert, L., Bell, R.: Performance tuning of adaptive wormhole routing through selection function choice. J. Parallel Distrib. Comput. 62(7), 1121–1141 (2002)

    Article  Google Scholar 

  20. Tang, M., Lin, X., Palesi, M.: Routing pressure: a channel-related and traffic-aware metric of routing algorithm. IEEE Trans. Parallel Distrib. Syst. 26(3), 891–901 (2015)

    Article  Google Scholar 

  21. Tang, M., Lin, X., Palesi, M.: The repetitive turn model for adaptive routing. IEEE Trans. Comput. 66(1), 138–146 (2017)

    Article  MathSciNet  Google Scholar 

  22. Xiang, D.: Deadlock-free adaptive routing in meshes with fault-tolerance ability based on channel overlapping. IEEE Trans. Dependable Sec. Comput. 8(1), 74–88 (2011)

    Article  Google Scholar 

  23. Yu, Z., Wang, X., Shen, K., Liu, H.: A general methodology to design deadlock-free routing algorithms for mesh networks. In: 15th International Conference on Algorithms and Architectures for Parallel Processing - ICA3PP, pp. 478–491. Springer, Zhangjiajie (2015)

    Chapter  Google Scholar 

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Author information

Authors and Affiliations

  1. School of Software, Tsinghua University, Beijing, 100084, China

    Yuan Cai & Xiang Ji

Authors
  1. Yuan Cai
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  2. Xiang Ji
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Corresponding author

Correspondence to Yuan Cai .

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Editors and Affiliations

  1. Rutgers University, Newark, NJ, USA

    Jaideep Vaidya

  2. Guangzhou University, Guangzhou, China

    Jin Li

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Cai, Y., Ji, X. (2018). ASA-routing: A-Star Adaptive Routing Algorithm for Network-on-Chips. In: Vaidya, J., Li, J. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2018. Lecture Notes in Computer Science(), vol 11335. Springer, Cham. https://doi.org/10.1007/978-3-030-05054-2_14

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  • DOI: https://doi.org/10.1007/978-3-030-05054-2_14

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-05053-5

  • Online ISBN: 978-3-030-05054-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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