Abstract
Advanced logic and physical synthesis tools provide numerous options and parameters that can drastically impact design quality; however, the large number of options leads to a complex design space difficult for human designers to navigate. By employing intelligent search strategies and parallel computing we can tackle this parameter tuning problem, thus automating one of the key design tasks conventionally performed by a human designer. To fully utilize the optimization potential of these tools, we propose SynTunSys, a system that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis parameter tuning process, i.e., job submission, results analysis, and next-step decision making, automating one of the more difficult decision processes faced by designers. This system has been employed for optimizing multiple IBM high-performance server chips and presents numerous opportunities for future intelligent automation research.
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Notes
- 1.
A macro, also referred to as a partition, is a separately synthesized component that is integrated into a larger chip. Macros considered in this chapter may span in size from 1K to 1M gates.
- 2.
The typical timing metrics of interest are: (1) internal slack or latch-to-latch slack (L2L), (2) worst negative slack (WNS), and (3) total negative slack (TNS).
- 3.
The server chips described in this chapter often go through two chip releases, a.k.a. tapeouts. The first tapeout is less optimized early version of the chip, whereas the second tapeout targets an optimized production quality chip.
- 4.
While many more configurations are possible, this experiment illustrates our initial attempt to configure the Learning algorithm parameters. Over time we have performed additional configuration experiments and designers running SynTunSys can also reconfigure the Learning algorithm as needed via the Rules file.
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Ziegler, M.M. et al. (2019). SynTunSys: A Synthesis Parameter Autotuning System for Optimizing High-Performance Processors. In: Elfadel, I., Boning, D., Li, X. (eds) Machine Learning in VLSI Computer-Aided Design. Springer, Cham. https://doi.org/10.1007/978-3-030-04666-8_18
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