Abstract
Memory design specifications typically include yield requirements, apart from performance and power requirements. These yield requirements are usually specified for the entire memory array at some supply voltage and temperature conditions. For example, the designer may be comfortable with an array failure probability of one in a thousand at 100∘C and 1 V supply, i.e., F f,array ≤ 10−3. However, how does this translate to a yield requirement for the memory cell? How do we even estimate the statistical distribution of memory cell performance metrics in this extreme rare event regime? We will answer these questions and in the process see the application of certain machine learning techniques and extreme value theory in memory design.
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To put this in perspective, note that achieving 99% yield for even 1000 bitcells requires marginal yield of 99.999% on each cell. For a parameter with an unskewed Gaussian distribution, this equates to over 4.2 standard deviations beyond the mean, far above the 2.3 assumed by a 99th percentile value. With mega-bits of memory, it is clear that assuming thresholds far into the tail is reasonable.
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This work was supported by the MARCO/DARPA Focus Research Center for Circuit and System Solutions (C2S2) and the Semiconductor Research Corporation.
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Singhee, A. (2019). Extreme Statistics in Memories. In: Elfadel, I., Boning, D., Li, X. (eds) Machine Learning in VLSI Computer-Aided Design. Springer, Cham. https://doi.org/10.1007/978-3-030-04666-8_10
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