Abstract
Underwater communication channels are designed to provide maximum data rate and its based on OFDM modules. Error coding which is an integral part of OFDM performs the process of error encoding and message decoding by convolution encoding and viterbi decoding respectively. With low power design requirement of OFDM modules for underwater applications, viterbi decoder iterative logic is designed and implemented on FPGA. The novel architecture for viterbi decoder is basically on LUT approach and direct decoding method. The dynamic reconfiguration of such a decoder works on threshold logic that is set with two threshold levels. The design implemented on FPGA is found to operate upto 188 Mbps data rate consuming less than 680 mW of power dissipation.
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Girish, N., Veena, M.B. (2019). 180 Mbps Viterbi Decoder Design on FPGA for OFDM Modulator in Underwater Communication Applications. In: Hemanth, J., Fernando, X., Lafata, P., Baig, Z. (eds) International Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 2018. ICICI 2018. Lecture Notes on Data Engineering and Communications Technologies, vol 26. Springer, Cham. https://doi.org/10.1007/978-3-030-03146-6_35
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DOI: https://doi.org/10.1007/978-3-030-03146-6_35
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