Abstract
A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. Simulations show that the new circuit can resolve input currents differing by less than 1μA with a negligible loss of operating speed. Detailed simulations and preliminary measured results of a single WTA cell and of a complete 8-input tree WTA network are presented.
This is a preview of subscription content, log in via an institution.
Preview
Unable to display preview. Download preview PDF.
References
R. Lippmann, “An introduction to computing with neural nets,” IEEE ASSP Mag., vol. 4, pp. 4–22, Apr 1987.
J. Ramirez-Angulo, “Building blocks for fuzzy processors,” IEEE Circuits & Devices Mag., vol. 10, pp. 48–50, Jul. 1994.
D. Grant, J. Taylor, and P. Houselander, “Design, implementation and evaluation of a high-speed integrated Hamming neural classifier,” IEEE J. Solid-State Circuits”, vol. 29, pp. 1154–1157, Sep. 1994.
J. Choi and B. Sheu, “A high-precision VLSI winner-take-all circuit for self-organising neural networks,” IEEE J. Solid-State Circuits, vol. 28, pp. 576–584, May 1993.
U. Cilingiroglu, “A charge-based neural Hamming classifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 59–67, Jan. 1993.
S. Smedley, J. Taylor, and M. Wilby, “A scalable high-speed current-mode winner-take-all network for VLSI neural applications,” IEEE Trans. Circuits and Systems-Part I, vol. 42, pp. 289–291, May 1995.
K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. USA: McGraw-Hill, 1994, pp. 385–386.
G. Di Cataldo, G. Palumbo and S. Stivala, “New CMOS current mirrors with improved high-frequency response,” Int. J. Circuit Theory and Applications, pp. 443–450, 1993.
C. Das, “MIETEC 2.4 μm CMOS MPC — Electrical parameters,” EUROCHIP Service Org. (RAL), Didcot, UK, Doc. MIE/F/02, Jan. 1993.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1996 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Demosthenous, A., Taylor, J., Smedley, S. (1996). A high-speed scalable CMOS current-mode Winner-Take-All network. In: von der Malsburg, C., von Seelen, W., Vorbrüggen, J.C., Sendhoff, B. (eds) Artificial Neural Networks — ICANN 96. ICANN 1996. Lecture Notes in Computer Science, vol 1112. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61510-5_65
Download citation
DOI: https://doi.org/10.1007/3-540-61510-5_65
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-61510-1
Online ISBN: 978-3-540-68684-2
eBook Packages: Springer Book Archive