Abstract
The Neural-RISC architecture consists of a primitive microprocessor and a parallel architecture, designed to optimise the computation of neural network models. The Neural-RISC system architecture consists of linear arrays of microprocessors connected in rings. Rings end up in an interconnecting module forming a cluster. Clusters of rings are arranged in different point-to-point topologies and are controlled by a host computer. The Neural-RISC node architecture comprises a 16-bit reduced instruction-set processor, a communication unit, and local memory—all integrated into the same silicon die. A VLSI prototype chip was implemented to demonstrate the system and node architecture. Using the standard 2μ CMOS technology, the chip integrates an array of two Neural-RISC microprocessors. This paper discusses the Neural-RISC design issues, presents a system overview and describes the VLSI implementation.
This work was supported by: CAPES and CNPq, Research Funding Agencies, Brazil; the British Council; LABO.
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© 1993 Springer-Verlag Berlin Heidelberg
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Pacheco, M., Treleaven, P. (1993). A risc architecture to support neural net simulation. In: Mira, J., Cabestany, J., Prieto, A. (eds) New Trends in Neural Computation. IWANN 1993. Lecture Notes in Computer Science, vol 686. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56798-4_192
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DOI: https://doi.org/10.1007/3-540-56798-4_192
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