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Extracting Exact Time Bounds from Logical Proofs

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Logic Based Program Synthesis and Transformation (LOPSTR 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2372))

Abstract

Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.

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Author information

Authors and Affiliations

  1. Dipartimento di Scienze dell’Informazione, Università degli Studi di Milano, Italy

    Mauro Ferrari, Camillo Fiorentini & Mario Ornaghi

Authors
  1. Mauro Ferrari
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  2. Camillo Fiorentini
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  3. Mario Ornaghi
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Editor information

Editors and Affiliations

  1. University of Rome Tor Vergata, Via del Politecnico 1, 00133, Rome, Italy

    Alberto Pettorossi

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© 2002 Springer-Verlag Berlin Heidelberg

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Ferrari, M., Fiorentini, C., Ornaghi, M. (2002). Extracting Exact Time Bounds from Logical Proofs. In: Pettorossi, A. (eds) Logic Based Program Synthesis and Transformation. LOPSTR 2001. Lecture Notes in Computer Science, vol 2372. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45607-4_14

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  • DOI: https://doi.org/10.1007/3-540-45607-4_14

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43915-8

  • Online ISBN: 978-3-540-45607-0

  • eBook Packages: Springer Book Archive

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