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Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4148))

Abstract

This paper introduces two low power design techniques to improve both the jitter and phase noise of PLL frequency synthesizers used in ASICs. These techniques focus on the noise current reduction in wideband ring VCOs. Two PLLs embedding such VCOs were implemented, in 0.18μm and 0.13μm CMOS technologies, under 1.8V and 1.2V supply voltages respectively. The maximum improvement was observed for a 1.8V PLL running at 160MHz and consuming 1.6mW, which phase noise was reduced from -81.4dBc/Hz to -88.4dBc/Hz.

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References

  1. Razavi, B.: Design of Analog CMOS Integrated Circuits. McGraw-Hill, New York (2001)

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  2. Hajimiri, A., Lee, T.H.: A General Theory of Phase Noise in Electrical Oscillators. IEEE Journal of Solid State Circuits 33(2), 179–194 (1998)

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  3. Hajimiri, A., Limotyrakis, S., Lee, T.H.: Jitter and Phase Noise in Ring Oscillators . IEEE Journal of Solid State Circuits 34(6), 790–804 (1999)

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  4. Ye, S., Jansson, L., Galton, I.: A Multiple-Crystal Interface PLL with VCO Realignment to Reduce Phase Noise. IEEE Journal of Solid State Circuits 37(12), 790–804 (2002)

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  5. Roubadia, R.: Theory and Design of a PLL using a realigned VCO. Master’s thesis, Univ. Montpellier 2 (2004)

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  6. Roubadia, R., Ajram, S.: Multi-Phase Realigned Voltage-Controlled Oscillator and Phase-Locked Loop Incorporating the same. Pending patent (April 2004)

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© 2006 Springer-Verlag Berlin Heidelberg

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Roubadia, R., Ajram, S., Cathébras, G. (2006). Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_44

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  • DOI: https://doi.org/10.1007/11847083_44

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-39094-7

  • Online ISBN: 978-3-540-39097-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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