Abstract
In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Kumar, S., Jantsch, A., Soinien, J.-P., Forsell, M., Millberg, M., Tiensyrjä, J., Hemani, A.: A network on chip architecture and design methodology. In: Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp. 117–124 (2002)
Thomas, A., Becker, J.: Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. In: IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI 2005), pp. 118–123 (2005)
Hollstein, T., Zimmer, H., Murgan, T., Glesner, M.: Flexible Communication-centric System-on-Chip Platforms for Ambient Appliances. In: ITG-Fachtagung Ambient Intelligence, pp. 127–132 (October 2004)
Langen, D., Niemann, J.-C., Porrmann, M., Kalte, H., Rückert, U.: Implementation of a RISC Processor Core for SoC Designs FPGA Prototype vs. ASIC Implementation. In: Proc. of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany (2002)
Grünewald, M., Kastens, U., Le, D.K., Niemann, J., Porrmann, M., Rückert, U., Thies, M., Slowik, A.: Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. In: PARELEC 2004, International Conference on Parallel Computing in Electrical Engineering, Dresden, Germany, pp. 209–214 (2004)
Kastens, U., Le, D.K., Slowik, A., Thies, M.: Feedback Driven Instruction-Set Extension. In: Proceedings of ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C., USA (June 2004)
Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proceedings of the Design Automation Conference, Las Vegas, Nevada, USA, pp. 684–689 (2001)
Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks: An Engineering Approach. IEEE Computer Society Press, Los Alamitos (1997)
Zhonghai, L., Jantsch, A.: Flit admission in on-chip wormhole-switched networks with virtual channels. In: Proc. of the International Symposium on Systems-on-Chip (2003)
Niemann, J., Porrmann, M., Rückert, U.: A Scalable Parallel SoC Architecture for Network Processors. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA (2005)
Silicore Inc. WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores. B.3 Edition (September 2002)
Kalte, H., Porrmann, M., Rückert, U.: A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. In: Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany (2002)
Niemann, J., Porrmann, M., Sauer, C., Rückert, U.: An Evaluation of the Scalable GigaNetIC Architecture for Access Networks. In: Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the ISCA 2005 (2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Niemann, JC., Puttmann, C., Porrmann, M., Rückert, U. (2006). GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. In: Grass, W., Sick, B., Waldschmidt, K. (eds) Architecture of Computing Systems - ARCS 2006. ARCS 2006. Lecture Notes in Computer Science, vol 3894. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11682127_19
Download citation
DOI: https://doi.org/10.1007/11682127_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-32765-3
Online ISBN: 978-3-540-32766-0
eBook Packages: Computer ScienceComputer Science (R0)