# Timing

• Sachin Sapatnekar
Book

1. Front Matter
Pages i-x
2. Pages 1-3
3. Pages 5-32
4. Pages 33-70
5. Pages 71-96
6. Pages 97-112
7. Pages 113-132
8. Pages 133-150
9. Pages 151-179
10. Pages 181-206
11. Pages 207-248
12. Pages 249-250
13. Back Matter
Pages 259-294

### Introduction

Statistical timing analysis is an area of growing importance in nanometer te- nologies‚ as the uncertainties associated with process and environmental var- tions increase‚ and this chapter has captured some of the major efforts in this area. This remains a very active field of research‚ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits‚ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book‚ the reader is referred to [LNPS00‚ HN01‚ JH01‚ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.

### Keywords

computer-aided design (CAD) interconnect layout optimization simulation transistor

#### Authors and affiliations

• Sachin Sapatnekar
• 1
1. 1.University of MinnesotaUSA

### Bibliographic information

• DOI https://doi.org/10.1007/b117318