Integrated Circuit and System Design

1. Session 3: Low Power (I)

   1. Reducing Cross-Talk Induced Power Consumption and Delay

      • André K. Nieuwland, Atul Katoch, Maurice Meijer

      Pages 179-188

   2. Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell

      • Ilham Hassoune, Amaury Neve, Jean-Didier Legat, Denis Flandre

      Pages 189-197

   3. Leakage Power Analysis and Comparison of Deep Submicron Logic Gates

      • Geoff Merrett, Bashir M. Al-Hashimi

      Pages 198-207

2. Session 4: Architectures

   1. Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS

      • Jie Ruan, Mark G. Arnold

      Pages 208-217

   2. Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications

      • Armin Wellig, Julien Zory, Norbert Wehn

      Pages 218-227

   3. Register Isolation for Synthesizable Register Files

      • Matthias Müller, Andreas Wortmann, Dominik Mader, Sven Simon

      Pages 228-237

   4. Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures

      • C. Brandolese, W. Fornaciari, F. Salice

      Pages 238-247

   5. Design of High-Speed Low-Power Parallel-Prefix VLSI Adders

      • G. Dimitrakopoulos, P. Kolovos, P. Kalogerakis, D. Nikolos

      Pages 248-257

3. Session 5: Asynchronous Circuits

   1. GALSification of IEEE 802.11a Baseband Processor

      • Miloš Krstić, Eckhard Grass

      Pages 258-267

   2. TAST Profiler and Low Energy Asynchronous Design Methodology

      • Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin

      Pages 268-277

   3. Low Latency Synchronization Through Speculation

      • D. J. Kinniment, A. V. Yakovlev

      Pages 278-288

   4. Minimizing the Power Consumption of an Asynchronous Multiplier

      • Yijun Liu, Steve Furber

      Pages 289-300

   5. A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling

      • T. Bjerregaard, S. Mahadevan, J. Sparsø

      Pages 301-310

4. Session 6: System Design

   1. L0 Cluster Synthesis and Operation Shuffling

      • Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck

      Pages 311-321

   2. On Combined DVS and Processor Evaluation

      • Anders Brødløs Olsen, Finn Büttner, Peter Koch

      Pages 322-331

   3. A Multi-level Validation Methodology for Wireless Network Applications

      • C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki

      Pages 332-341

   4. SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level

      • Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin

      Pages 342-351

   5. Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards

      • Emanuele Lattanzi, Andrea Acquaviva, Alessandro Bogliolo

      Pages 352-361

   6. Towards a Software Power Cost Analysis Framework Using Colored Petri Net

      • Meuse N. Oliveira Júnior, Paulo R. Martins Maciel, Raimundo S. Barreto, Fernando F. Carvalho

      Pages 362-371

5. Session 7: Circuits and Devices (II)

   1. A 260ps Quasi-static ALU in 90nm CMOS

      • F. Pessolano, R. I. M. P. Meijer

      Pages 372-380

WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.

• CAD design tools
• SoC systems
• circuit design
• computer architecture
• computer systems design
• integrated circuit design
• low power design
• modeling
• optimization
• performance analysis
• power-efficient design
• processor architecture
• systems modeling
• systems performance

• Politecnico di Torino, Torino, Italy

  Enrico Macii

• Electrical and Computer Engineering Department, University of Patras, Greece

  Vassilis Paliouras

• Department of Electrical and Computer Engineering, University of Patras, Patras, Greece

  Odysseas Koufopavlou

Policies and ethics