Advances in Computer Systems Architecture

9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings

  • Pen-Chung Yew
  • Jingling Xue
Conference proceedings ACSAC 2004

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3189)

Table of contents

  1. Front Matter
  2. Keynote Address I

  3. Session 1A: Cache and Memory

    1. Chunrong Lai, Shih-Lien Lu
      Pages 16-29
    2. Xingyan Tian, Kejia Zhao, Huowang Chen, Hongyan Du
      Pages 30-43
    3. Diego Andrade, Basilio B. Fraguela, Ramón Doallo
      Pages 44-57
  4. Session 1B: Reconfigurable and Embedded Architectures

    1. Nicolas Ventroux, Stéphane Chevobbe, Fréderic Blanc, Thierry Collette
      Pages 72-87
    2. Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
      Pages 88-101
  5. Session 2A: Processor Architecture and Design I

    1. Jian Chen, Ruhao Xu, Yuzhuo Fu
      Pages 115-125
    2. Lei Wang, Hong-yi Lu, Kui Dai, Zhi-ying Wang
      Pages 126-136
    3. Wenbin Yao, Dongsheng Wang, Weimin Zheng
      Pages 137-145
  6. Session 2B: Power and Energy Management

  7. Session 3A: Processor Architecture and Design II

    1. Marc Epalza, Paolo Ienne, Daniel Mlynek
      Pages 185-198
    2. Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang
      Pages 199-211
    3. Kentaro Hamayasu, Vasily G. Moshnyaga
      Pages 212-225
  8. Session 3B: Compiler and Operating System Issues

About these proceedings

Introduction

On behalf of the program committee, we were pleased to present this year’s program for ACSAC: Asia-Paci?c Computer Systems Architecture Conference. Now in its ninth year, ACSAC continues to provide an excellent forum for researchers, educators and practitioners to come to the Asia-Paci?c region to exchange ideas on the latest developments in computer systems architecture. This year, the paper submission and review processes were semiautomated using the free version of CyberChair. We received 152 submissions, the largest number ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee members for review. All of the papers were reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the review process. When reviewers claimed inadequate expertise, additional reviewers were solicited. In the end, we received a total of 594 reviews (3.9 per paper) from committee members as well as 248 coreviewers whose names are acknowledged in the proceedings. We would like to thank all of them for their time and e?ort in providing us with such timely and high-quality reviews, some of them on extremely short notice.

Keywords

EPIC Random Access Memory Scheduling computer architecture device driver driver high-performance architecture interconnection networks microarchitectures network computing operating system parallel architectures processor system-on-chip architecture virtual machine

Editors and affiliations

  • Pen-Chung Yew
    • 1
  • Jingling Xue
    • 2
  1. 1.Department of Computer ScienceUniversity of MinnesotaMinneapolis
  2. 2.National ICTAustralia

Bibliographic information

  • DOI https://doi.org/10.1007/b100354
  • Copyright Information Springer-Verlag Berlin Heidelberg 2004
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-23003-8
  • Online ISBN 978-3-540-30102-8
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book