Editors:
Includes supplementary material: sn.pub/extras
Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3189)
Conference series link(s): ACSAC: Asia-Pacific Conference on Advances in Computer Systems Architecture
Conference proceedings info: ACSAC 2004.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsThis is a preview of subscription content, access via your institution.
Table of contents (48 papers)
-
Front Matter
-
Keynote Address I
-
Session 1A: Cache and Memory
-
Session 1B: Reconfigurable and Embedded Architectures
-
Session 2A: Processor Architecture and Design I
-
Session 2B: Power and Energy Management
-
Session 3A: Processor Architecture and Design II
-
Session 3B: Compiler and Operating System Issues
About this book
Keywords
- EPIC
- Random Access Memory
- Scheduling
- computer architecture
- device driver
- driver
- high-performance architecture
- interconnection networks
- microarchitectures
- network computing
- operating system
- parallel architectures
- processor
- system-on-chip architecture
- virtual machine
Editors and Affiliations
-
Department of Computer Science, University of Minnesota, Minneapolis
Pen-Chung Yew
-
National ICT, Australia
Jingling Xue
Bibliographic Information
Book Title: Advances in Computer Systems Architecture
Book Subtitle: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings
Editors: Pen-Chung Yew, Jingling Xue
Series Title: Lecture Notes in Computer Science
DOI: https://doi.org/10.1007/b100354
Publisher: Springer Berlin, Heidelberg
-
eBook Packages: Springer Book Archive
Copyright Information: Springer-Verlag Berlin Heidelberg 2004
Softcover ISBN: 978-3-540-23003-8Published: 14 September 2004
eBook ISBN: 978-3-540-30102-8Published: 19 August 2004
Series ISSN: 0302-9743
Series E-ISSN: 1611-3349
Edition Number: 1
Number of Pages: XVIII, 602
Topics: Computer System Implementation, Arithmetic and Logic Structures, Input/Output and Data Communications, Register-Transfer-Level Implementation, Computer Communication Networks, Processor Architectures