Real-Time BCI System Design to Control Arduino Based Speed Controllable Robot Using EEG

This book discusses the basic requirements and constraints in building a brain–computer interaction system. These include the technical requirements for building the signal processing module and the acquisition module. The major aspects to be considered when designing a signal acquisition module for a brain–computer interaction system are the human brain, types and applications of brain–computer systems, and the basics of EEG (electroencephalogram) recording. The book also compares the algorithms that have been and that can be used to design the signal processing module of brain–computer interfaces, and describes the various EEG-acquisition devices available and compares their features and inadequacies. Further, it examines in detail the use of Emotiv EPOC (an EEG acquisition module developed by Emotiv) to build a complete brain–computer interaction system for driving robots using a neural network classification module.

• Brain-Computer interaction
• BCI applications
• Sensorimotor activity
• SIMULINK EEG Importer
• BCI algorithms

• Machine Vision Laboratory, CSIR-Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, India

  Swagata Das, Devashree Tripathy, Jagdish Lal Raheja

Swagata Das is pursuing her PhD in Biological Systems Engineering at Hiroshima University, Japan, having completed her M.Tech. in Electronics Design and Technology, for which she received a gold medal, at Tezpur Central University, Assam, India. She was also awarded gold medals by His Excellency Late Dr. A. P. J. Abdul Kalam, Ex-President of India and Shri. Kapil Sibal, ex-Union Minister of India for her exceptional performance in academics at NERIST, Itanagar, India. Her research interests include electronics applications of mathematical modeling and brain–computer interaction. She has published her research work in Springer and IEEE proceedings.

Devashree Tripathi completed her M.Tech. in Advanced Electronics Systems at CSIR-Central Electronics Engineering Research Institute. Currently she is a PhD candidate at the Department of Computer Science & Engineering at the University of California, Riverside and also a member of the SoCal Lab at UCR. Her research interests include computer architecture, GPGPU architecture design, high-performance computing, and fault-tolerance systems. She has worked on multiple projects on data-dependent applications on GPGPU, low power design of GPGPU execution units and has achieved notable improvements in terms of performance gain and power and area saving. She has published papers in respected journals and conferences.

Jagdish Lal Raheja is a Senior Principal Scientist and Professor at the CSIR-Central Electronics Engineering Research Institute (CSIR-CEERI). Previously, he was also a Visiting Scientist at the University of Maribor, Slovenia and a Guest Scientist at the Technical University Dortmund, Germany, University College London, and the Fraunhofer-Institutszentrum Schloss Birlinghoven. His areas of specialization are image processing, pattern recognition, perception engineering, digital cartographic generalization and artificial intelligence, and he has completed numerous research projects in these areas. He has published in various high impact journals and conference proceedings. He is also an editorial board member and reviewer for several journals and conferences.