# VLSI Planarization

## Methods, Models, Implementation

• V. Feinberg
• A. Levin
• E. Rabinovich
Book

Part of the Mathematics and Its Applications book series (MAIA, volume 399)

1. Front Matter
Pages i-vi
2. V. Feinberg, A. Levin, E. Rabinovich
Pages 1-5
3. V. Feinberg, A. Levin, E. Rabinovich
Pages 7-25
4. V. Feinberg, A. Levin, E. Rabinovich
Pages 27-43
5. V. Feinberg, A. Levin, E. Rabinovich
Pages 45-86
6. V. Feinberg, A. Levin, E. Rabinovich
Pages 87-97
7. V. Feinberg, A. Levin, E. Rabinovich
Pages 99-120
8. V. Feinberg, A. Levin, E. Rabinovich
Pages 121-132
9. V. Feinberg, A. Levin, E. Rabinovich
Pages 133-171
10. Back Matter
Pages 173-186

### Introduction

At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun­ nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer­ aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it.

### Keywords

Hypergraph Mathematica VLSI algorithms circuit complexity complexity theory computer development graph theory mathematics

#### Authors and affiliations

• V. Feinberg
• 1
• A. Levin
• 2
• E. Rabinovich
• 3
1. 1.SILVACO InternationalSanta ClaraUSA
2. 2.Intel CorporationSanta ClaraUSA
3. 3.GorizontMinskBelarus

### Bibliographic information

• DOI https://doi.org/10.1007/978-94-011-5740-7