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VLSI Physical Design: From Graph Partitioning to Timing Closure

  • Andrew B. Kahng
  • Jens Lienig
  • Igor L. Markov
  • Jin Hu

Table of contents

  1. Front Matter
    Pages 1-10
  2. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 1-30
  3. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 31-54
  4. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 55-92
  5. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 93-128
  6. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 129-166
  7. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 167-188
  8. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 189-218
  9. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
    Pages 219-264
  10. Back Matter
    Pages 275-318

About this book

Introduction

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.

"VLSI Physical Design: From Graph Partitioning to Timing Closure"
introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

Keywords

EDA Electronic Design Automation Electronics Physical design algorithms VLSI design chip planning design automation partitioning placement routing time closure

Authors and affiliations

  • Andrew B. Kahng
    • 1
  • Jens Lienig
    • 2
  • Igor L. Markov
    • 3
  • Jin Hu
    • 4
  1. 1., Depts of CSE and ECEUniversity of California San DiegoLa JollaUSA
  2. 2.Technology, Electrical Engineering and InformationDresden University of TechnologyDresdenGermany
  3. 3.Electrical Engineering &, Computer ScienceUniversity of MichiganAnn ArborUSA
  4. 4.Electrical Engineering &, Computer ScienceUniversity of MichiganAnn ArborUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-90-481-9591-6
  • Copyright Information Springer Science+Business Media B.V. 2011
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-90-481-9590-9
  • Online ISBN 978-90-481-9591-6
  • Buy this book on publisher's site