Third Caltech Conference on Very Large Scale Integration

  • Randal Bryant

Table of contents

  1. Front Matter
    Pages i-xii
  2. Invited Papers

    1. Front Matter
      Pages xiii-xiii
    2. Egon Hörbst, Gerd Sandweg, Stefan Wallstab
      Pages 1-13
    3. John L. Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross
      Pages 33-54
  3. Circuit Timing

    1. Front Matter
      Pages N3-N3
    2. John K. Ousterhout
      Pages 57-69
    3. Norman P. Jouppi
      Pages 71-85
    4. Charles E. Leiserson, Flavio M. Rose, James B. Saxe
      Pages 87-116
  4. Routing and Interconnection

    1. Front Matter
      Pages N5-N5
    2. Wan S. Chan
      Pages 117-139
    3. Ron Y. Pinter
      Pages 141-163
    4. Jonathan W. Greene, Abbas EI Gamal
      Pages 165-184
  5. Formal System Models

    1. Front Matter
      Pages N7-N7
    2. Robert E. Shostak
      Pages 185-206
    3. Marina C. Chen, Carver A. Mead
      Pages 207-223
    4. Martin Rem, Jan L. A. van de Snepscheut, Jan Tijmen Udding
      Pages 225-239
    5. Jan L. A. van de Snepscheut
      Pages 241-256
  6. System Building Blocks

    1. Front Matter
      Pages N9-N9
    2. Alan B. Hayes
      Pages 257-274
    3. Edward H. Frank, Robert F. Sproull
      Pages 275-285
    4. Allan L. Fisher, H. T. Kung, Louis M. Monier, Hank Walker, Yasunori Dohi
      Pages 287-302
  7. Special-Purpose Chip Architectures

    1. Front Matter
      Pages N11-N11
    2. T. K. Truong, L. J. Deutsch, I. S. Reed, I. S. Hsu, K. Wang, C. S. Yeh
      Pages 303-329
    3. Jonathan Schaeffer, P. A. D. Powell, Jim Jonkman
      Pages 331-350
    4. Joseph Ja’Ja’, Robert Michael Owens
      Pages 351-377
  8. Silicon Compilation

    1. Front Matter
      Pages N13-N13
    2. Wayne Wolf, John Newkirk, Robert Mathews, Robert Dutton
      Pages 379-393
    3. Stephen P. Pope, R. W. Brodersen
      Pages 395-412

About these proceedings


The papers in this book were presented at the Third Caltech Conference on Very Large Scale Integration, held March 21-23, 1983 in Pasadena, California. The conference was organized by the Computer Science Depart­ ment, California Institute of Technology, and was partly supported by the Caltech Silicon Structures Project. This conference focused on the role of systematic methodologies, theoretical models, and algorithms in all phases of the design, verification, and testing of very large scale integrated circuits. The need for such disciplines has arisen as a result of the rapid progress of integrated circuit technology over the past 10 years. This progress has been driven largely by the fabrica­ tion technology, providing the capability to manufacture very complex elec­ tronic systems reliably and at low cost. At this point the capability to manufac­ ture very large scale integrated circuits has exceeded our capability to develop new product designs quickly, reliably, and at a reasonable cost. As a result new designs are undertaken only if the production volume will be large enough to amortize high design costs, products first appear on the market well past their announced delivery date, and reference manuals must be amended to document design flaws. Recent research in universities and in private industry has created an emerg­ ing science of very large scale integration.


Integrierte Schaltung Schaltung VLSI integrated circuit production

Editors and affiliations

  • Randal Bryant
    • 1
  1. 1.California Institute of TechnologyUSA

Bibliographic information

  • DOI
  • Copyright Information Springer-Verlag Berlin Heidelberg 1983
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-12369-9
  • Online ISBN 978-3-642-95432-0
  • Buy this book on publisher's site