Computer Engineering and Technology

1. Front Matter

   PDF

2. Session 1: Microprocessor and Implementation

   1. A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU

      • Zhuo Ma, Zhenyu Zhao, Yang Guo, Lunguo Xie, Jinshan Yu

      Pages 1-7

   2. Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method

      • Shengfei Wu, Jiang Jiang, Yuzhuo Fu

      Pages 8-15

   3. MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor

      • Xiaobo Yan, Rangyu Deng, Caixia Sun, Qiang Dou

      Pages 16-26

   4. An Efficient Parallel SURF Algorithm for Multi-core Processor

      • Zhong Liu, Binchao Xing, Yueyue Chen

      Pages 27-37

   5. A Study of Cache Design in Stream Processor

      • Chiyuan Ma, Zhenyu Zhao

      Pages 38-48

   6. Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor

      • Chuan Zhou, Yuzhuo Fu, Jiang Jiang, Xing Han, Kaikai Yang

      Pages 49-56

   7. Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture

      • Ziyang Liu, Yuzhuo Fu, Jiang Jiang, Xing Han

      Pages 57-66

   8. ADL and High Performance Processor Design

      • Liu Yang, Xiaoqiang Ni, Yusong Tan, Hengzhu Liu

      Pages 67-74

3. Session 2: Design of Integration Circuit

   1. The Design of the ROHC Header Compression Accelerator

      • Mengmeng Yan, Shengbing Zhang

      Pages 75-83

   2. A Hardware Implementation of Nussinov RNA Folding Algorithm

      • Qilong Su, Jiang Jiang, Yuzhuo Fu

      Pages 84-91

   3. A Configurable Architecture for 1-D Discrete Wavelet Transform

      • Qing Sun, Jiang Jiang, Yuzhuo Fu

      Pages 92-101

   4. A Comparison of Folded Architectures for the Discrete Wavelet Transform

      • Jia Zhou, Jiang Jiang

      Pages 102-110

   5. A High Performance DSP System with Fault Tolerant for Space Missions

      • Kang Xia, Ao Shen, Yuzhuo Fu, Ting Liu, Jiang Jiang

      Pages 111-120

   6. The Design and Realization of Campus Information Release Platform Based on Android Framework

      • Jie Wang, Xue Yu, Yu Zeng, Dongri Yang

      Pages 121-128

   7. A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method

      • Yuan Li, Jiang Jiang, Minxuan Zhang, Shaojun Wei

      Pages 129-137

4. Session 3: I/O Interconnect

   1. DAMQ Sharing Scheme for Two Physical Channels in High Performance Router

      • Yongqing Wang, Minxuan Zhang

      Pages 138-147

   2. Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip

      • Peng Wu, Yuzhuo Fu, Jiang Jiang

      Pages 148-154

   3. HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip

      • Liguo Zhang, Huimin Du, Jianyuan Liu

      Pages 155-162

   4. Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator

      • Kaikai Yang, Yuzhuo Fu, Xing Han, Jiang Jiang

      Pages 163-172

This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.

• circuit design
• hardware implementation
• network on chip
• performance modeling and analysis
• processor architecture

• School of Computer Science, national University of Defense Technology, Changsha, P.R. China

  Weixia Xu

• School of Computer Science, National University of Defense Technology, Changsha, P.R. China

  Liquan Xiao, Pingjing Lu, Jinwen Li

• School of Computer Sciende, National University of Defense Technology, Changsha, P.R. China

  Chengyi Zhang

Policies and ethics