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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers

  • José Monteiro
  • René van Leuken
Conference proceedings PATMOS 2009

Part of the Lecture Notes in Computer Science book series (LNCS, volume 5953)

Table of contents

  1. Front Matter
  2. Keynotes

  3. Special Session

    1. Martin Barnasconi, Markus Damm, Karsten Einwich
      Pages 4-4
  4. Session 1: Variability & Statistical Timing

    1. Mohsen Raji, Behnam Ghavami, Hamid R. Zarandi, Hossein Pedram
      Pages 5-15
    2. Zeqin Wu, Philippe Maurine, Nadine Azemard, Gille Ducharme
      Pages 16-25
    3. Ioannis Kouretas, Vassilis Paliouras
      Pages 26-35
    4. Paul Zuber, Vladimir Matvejev, Philippe Roussel, Petr Dobrovolný, Miguel Miranda
      Pages 36-45
  5. Poster Session 1: Circuit Level Techniques

    1. Monica Figueiredo, Rui L. Aguiar
      Pages 46-55
    2. Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi
      Pages 56-65
    3. Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino
      Pages 66-75
    4. Javier Castro, Pilar Parra, Antonio J. Acosta
      Pages 76-85
  6. Session 2: Power Management

    1. Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris
      Pages 86-95
    2. Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino
      Pages 96-105
    3. Howard Chen, Indira Nair
      Pages 106-115
    4. Muhammad Khurram Bhatti, Muhammad Farooq, Cécile Belleudy, Michel Auguin, Ons Mbarek
      Pages 116-126
  7. Session 3: Low Power Circuits & Technology

    1. Ritej Bachhawat, Pankaj Golani, Peter A. Beerel
      Pages 136-145
    2. Tomasz Król, Milos Krstić, Xin Fan, Eckhard Grass
      Pages 146-155
    3. Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi
      Pages 156-164
  8. Poster Session 2: System Level Techniques

    1. Nikolaos Zompakis, Martin Trautmann, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris, Liesbet Van der Perre et al.
      Pages 165-174
    2. Alexandros Bartzas, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Fragkiskos Ieromnimon, Nikolaos S. Voros
      Pages 175-185
    3. Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid
      Pages 186-195
    4. Newsha Ardalani, Amirali Baniasadi
      Pages 196-205
    5. Marius Gligor, Nicolas Fournel, Frédéric Pétrot, Fabien Colas-Bigey, Anne-Marie Fouilliart, Philippe Teninge et al.
      Pages 206-215
    6. Tom English, Ka Lok Man, Emanuel Popovici
      Pages 216-226
  9. Session 4: Power & Timing Optimization Techniques

    1. Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
      Pages 227-236
    2. Thomas Schweizer, Julio Oliveira, Tommy Kuhn, Wolfgang Rosenstiel
      Pages 237-246
    3. Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, Abhishek Bansal et al.
      Pages 247-255
  10. Session 5: Self-timed Circuits

    1. Hossein Karimiyan Alidash, Vojin G. Oklobdzija
      Pages 256-265
    2. Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine et al.
      Pages 266-275
    3. Yuri Stepchenkov, Yuri Diachenko, Victor Zakharov, Yuri Rogdestvenski, Nikolai Morozov, Dmitri Stepchenkov
      Pages 276-285
    4. Delong Shang, Fei Xia, Stanislavs Golubcovs, Alex Yakovlev
      Pages 286-296
  11. Session 6: Low Power Circuit Analysis & Optimization

    1. Sidinei Ghissoni, Joao Batista dos Santos Martins, Ricardo Augusto da Luz Reis, Jose Carlos Monteiro
      Pages 297-306
    2. Milena Vratonjić, Matthew Ziegler, George D. Gristede, Victor Zyuban, Thomas Mitchell, Ee Cho et al.
      Pages 307-316
    3. Paulo F. Butzen, André I. Reis, Renato P. Ribas
      Pages 317-325
  12. Session 7: Low Power Design Studies

    1. Néstor Suárez, Gustavo M. Callicó, Roberto Sarmiento, Octavio Santana, Anteneh A. Abbo
      Pages 326-335
    2. Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
      Pages 336-346
    3. Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall
      Pages 347-356
  13. Back Matter

About these proceedings

Introduction

This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009.

The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.

 

Keywords

CMOS DSP FPGA NoC VLSI embedded systems integrated circuits modeling performance evalutation simulation systems design systems modelling

Editors and affiliations

  • José Monteiro
    • 1
  • René van Leuken
    • 2
  1. 1.INESC-ID / ISTTU LisbonLisbonPortugal
  2. 2.EEMCS/MECE/CASDelft University of TechnologyDelftThe Netherlands

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-642-11802-9
  • Copyright Information Springer-Verlag Berlin Heidelberg 2010
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-642-11801-2
  • Online ISBN 978-3-642-11802-9
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site