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High Performance Embedded Architectures and Compilers

Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings

  • Conference proceedings
  • © 2008

Overview

Editors:
  1. Per Stenström
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  2. Michel Dubois
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  3. Manolis Katevenis
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  4. Rajiv Gupta
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  5. Theo Ungerer
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4917)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: HiPEAC 2008.

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Table of contents (26 papers)

  1. Front Matter

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  2. Invited Program

    1. Front Matter

      Pages 1-1
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    2. Supercomputing for the Future, Supercomputing from the Past (Keynote)

      • Mateo Valero, Jesús Labarta
      Pages 3-5

  3. I Multithreaded and Multicore Processors

    1. Front Matter

      Pages 7-7
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    2. MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing

      • Kevin D. Kissell
      Pages 9-21

    3. rMPI: Message Passing on Multicore Processors with On-Chip Interconnect

      • James Psota, Anant Agarwal
      Pages 22-37

    4. Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE

      • Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos
      Pages 38-52

  4. IIa Reconfigurable - ASIP

    1. Front Matter

      Pages 53-53
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    2. BRAM-LUT Tradeoff on a Polymorphic DES Design

      • Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
      Pages 55-65

    3. Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array

      • Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev
      Pages 66-81

    4. Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP

      • Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael de Nil et al.
      Pages 82-96

  5. IIb Compiler Optimizations

    1. Front Matter

      Pages 97-97
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    2. Fast Bounds Checking Using Debug Register

      • Tzi-cker Chiueh
      Pages 99-113

    3. Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis

      • Stijn Eyerman, Lieven Eeckhout, James E. Smith
      Pages 114-129

    4. An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems

      • Marco Cornero, Roberto Costa, Ricardo Fernández Pascual, Andrea C. Ornstein, Erven Rohou
      Pages 130-144

  6. III Industrial Processors and Application Parallelization

    1. Front Matter

      Pages 145-145
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    2. Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions

      • Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal
      Pages 147-160

    3. Experiences with Parallelizing a Bio-informatics Program on the Cell BE

      • Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere
      Pages 161-175

    4. Drug Design Issues on the Cell BE

      • Harald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, Daniel Jiménez-González
      Pages 176-190

  7. IV Power-Aware Techniques

    1. Front Matter

      Pages 191-191
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