Advertisement

Architecture of Computing Systems – ARCS 2018

31st International Conference, Braunschweig, Germany, April 9–12, 2018, Proceedings

  • Mladen Berekovic
  • Rainer Buchty
  • Heiko Hamann
  • Dirk Koch
  • Thilo Pionteck
Conference proceedings ARCS 2018

Part of the Lecture Notes in Computer Science book series (LNCS, volume 10793)

Also part of the Theoretical Computer Science and General Issues book sub series (LNTCS, volume 10793)

Table of contents

  1. Front Matter
    Pages I-XV
    PDF

  2. Embedded Systems

    1. Front Matter
      Pages 1-1
      PDF
    2. Trade-Off Between Performance, Fault Tolerance and Energy Consumption in Duplication-Based Taskgraph Scheduling
      Patrick Eitschberger, Simon Holmbacka, Jörg Keller
      Pages 3-17
    3. Lipsi: Probably the Smallest Processor in the World
      Martin Schoeberl
      Pages 18-30
    4. Superlinear Scalability in Parallel Computing and Multi-robot Systems: Shared Resources, Collaboration, and Network Topology
      Heiko Hamann
      Pages 31-42

  3. Multicore Systems

    1. Front Matter
      Pages 43-43
      PDF
    2. Closed Loop Controller for Multicore Real-Time Systems
      Johannes Freitag, Sascha Uhrig
      Pages 45-56
    3. Optimization of the GNU OpenMP Synchronization Barrier in MPSoC
      Maxime France-Pillois, Jérôme Martin, Frédéric Rousseau
      Pages 57-69

  4. Analysis and Optimization

    1. Front Matter
      Pages 71-71
      PDF
    2. Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes
      Achim Lösch, Alex Wiens, Marco Platzner
      Pages 73-84
    3. A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model
      Sebastian Rachuj, Christian Herglotz, Marc Reichenbach, André Kaup, Dietmar Fey
      Pages 85-96

  5. On-chip and Off-chip Networks

    1. Front Matter
      Pages 97-97
      PDF
    2. A CAM-Free Exascalable HPC Router for Low-Energy Communications
      Caroline Concatto, Jose A. Pascual, Javier Navaridas, Joshua Lant, Andrew Attwood, Mikel Lujan et al.
      Pages 99-111
    3. Lightweight Hardware Synchronization for Avoiding Buffer Overflows in Network-on-Chips
      Martin Frieb, Alexander Stegmeier, Jörg Mische, Theo Ungerer
      Pages 112-126
    4. Network Optimization for Safety-Critical Systems Using Software-Defined Networks
      Cora Perner
      Pages 127-138
    5. CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms
      Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, Andreas Herkersdorf
      Pages 139-152

  6. Memory Models and Systems

    1. Front Matter
      Pages 153-153
      PDF
    2. Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional Memory
      Rico Amslinger, Sebastian Weis, Christian Piatka, Florian Haas, Theo Ungerer
      Pages 155-167
    3. Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy
      Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié
      Pages 168-180
    4. On Automated Feedback-Driven Data Placement in Multi-tiered Memory
      T. Chad Effler, Adam P. Howard, Tong Zhou, Michael R. Jantz, Kshitij A. Doshi, Prasad A. Kulkarni
      Pages 181-194
    5. Operational Characterization of Weak Memory Consistency Models
      M. Senftleben, K. Schneider
      Pages 195-208

  7. Energy Efficient Systems

    1. Front Matter
      Pages 209-209
      PDF
    2. A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode
      Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando
      Pages 211-224
    3. Performance-Energy Trade-off in CMPs with Per-Core DVFS
      Solomon Abera, M. Balakrishnan, Anshul Kumar
      Pages 225-238
    4. Towards Fine-Grained DVFS in Embedded Multi-core CPUs
      Giuseppe Massari, Federico Terraneo, Michele Zanella, Davide Zoni
      Pages 239-251

  8. Partial Reconfiguration

    1. Front Matter
      Pages 253-253
      PDF
    2. Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors
      Joost Hoozemans, Jeroen van Straten, Zaid Al-Ars, Stephan Wong
      Pages 255-268
    3. HLS Enabled Partially Reconfigurable Module Implementation
      Nicolae Bogdan Grigore, Charalampos Kritikakis, Dirk Koch
      Pages 269-282
    4. Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration
      Alexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik
      Pages 283-293

  9. Large Scale Computing

    1. Front Matter
      Pages 295-295
      PDF
    2. Do Iterative Solvers Benefit from Approximate Computing? An Evaluation Study Considering Orthogonal Approximation Methods
      Michael Bromberger, Markus Hoffmann, Robin Rehrmann
      Pages 297-310
    3. A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks
      Thorbjörn Posewsky, Daniel Ziener
      Pages 311-323
  10. Back Matter
    Pages 325-326
    PDF

About these proceedings

Introduction

This book constitutes the proceedings of the 31st International Conference on Architecture of Computing Systems, ARCS 2018, held in Braunschweig, Germany, in April 2018.

The 23 full papers presented in this volume were carefully reviewed and selected from 53 submissions. ARCS has always been a conference attracting leading-edge research outcomes in Computer Architecture and Operating Systems, including a wide spectrum of topics ranging from embedded and real-time systems all the way to large-scale and parallel systems.

Keywords

Computer systems organization Reconfigurable logic and FPGAs Embedded and cyber-physical systems Heterogeneous (hybrid) systems Multicore architectures Fault tolerance Dependable and fault-tolerant systems and networks Multicore architectures Self-organizing autonomic computing Tool support for performance optimization and debugging Power management Operating systems Programming models and runtimes Middleware Computer architecture Microprocessor chips Processors Wireless telecommunication networks Telecommunication traffic Wireless sensor networks

Editors and affiliations

  • Mladen Berekovic
    • 1
  • Rainer Buchty
    • 2
  • Heiko Hamann
    • 3
  • Dirk Koch
    • 4
  • Thilo Pionteck
    • 5
  1. 1.Chair for Chip Design for Embedded ComputingTechnische Universität BraunschweigBraunschweigGermany
  2. 2.Chair for Chip Design for Embedded ComputingTechnische Universität BraunschweigBraunschweigGermany
  3. 3.Institute of Computer EngineeringUniversität zu LübeckLübeckGermany
  4. 4.School of Computer ScienceThe University of ManchesterManchesterUnited Kingdom
  5. 5.Institute for Information Technology and CommunicationsOtto-von-Guericke Universität MagdeburgMagdeburgGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-77610-1
  • Copyright Information Springer International Publishing AG, part of Springer Nature 2018
  • Publisher Name Springer, Cham
  • eBook Packages Computer Science
  • Print ISBN 978-3-319-77609-5
  • Online ISBN 978-3-319-77610-1
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site