Testing of Interposer-Based 2.5D Integrated Circuits

  • Ran Wang
  • Krishnendu Chakrabarty

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Ran Wang, Krishnendu Chakrabarty
    Pages 1-15
  3. Ran Wang, Krishnendu Chakrabarty
    Pages 17-48
  4. Ran Wang, Krishnendu Chakrabarty
    Pages 49-80
  5. Ran Wang, Krishnendu Chakrabarty
    Pages 81-108
  6. Ran Wang, Krishnendu Chakrabarty
    Pages 109-133
  7. Ran Wang, Krishnendu Chakrabarty
    Pages 135-162
  8. Ran Wang, Krishnendu Chakrabarty
    Pages 163-178
  9. Ran Wang, Krishnendu Chakrabarty
    Pages 179-182

About this book

Introduction

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits.  The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies.  This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.

  • Provides a single-source guide to the practical challenges in testing of 2.5D ICs;
  • Presents an efficient method to locate defects in a passive interposer before stacking;
  • Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults;
  • Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard;
  • Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die;
  • Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.

Keywords

Physical Design for 3D Integrated Circuits 2.5D IC Testing Testing of the Silicon Interposer Testing Interposer Interconnects BIST architectures for interconnect and die testing

Authors and affiliations

  • Ran Wang
    • 1
  • Krishnendu Chakrabarty
    • 2
  1. 1.Nvidia (United States) SunnyvaleUSA
  2. 2.Department of ECEDuke University Department of ECEDurhamUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-54714-5
  • Copyright Information Springer International Publishing AG 2017
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-54713-8
  • Online ISBN 978-3-319-54714-5
  • About this book