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Digital VLSI Design with Verilog

A Textbook from Silicon Valley Polytechnic Institute

  • John Michael Williams

Table of contents

  1. Front Matter
    Pages i-xvi
  2. John Michael Williams
    Pages 1-12
  3. John Michael Williams
    Pages 13-38
  4. John Michael Williams
    Pages 39-66
  5. John Michael Williams
    Pages 67-88
  6. John Michael Williams
    Pages 89-113
  7. John Michael Williams
    Pages 115-132
  8. John Michael Williams
    Pages 133-146
  9. John Michael Williams
    Pages 147-181
  10. John Michael Williams
    Pages 183-209
  11. John Michael Williams
    Pages 211-229
  12. John Michael Williams
    Pages 231-243
  13. John Michael Williams
    Pages 245-261
  14. John Michael Williams
    Pages 263-285
  15. John Michael Williams
    Pages 287-300
  16. John Michael Williams
    Pages 301-321
  17. John Michael Williams
    Pages 323-344
  18. John Michael Williams
    Pages 345-362
  19. John Michael Williams
    Pages 363-380
  20. John Michael Williams
    Pages 381-413
  21. John Michael Williams
    Pages 415-444
  22. John Michael Williams
    Pages 445-467
  23. John Michael Williams
    Pages 469-505
  24. John Michael Williams
    Pages 507-515
  25. John Michael Williams
    Pages 517-523
  26. John Michael Williams
    Pages 525-542
  27. Back Matter
    Pages 543-553

About this book

Introduction

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics includes SystemVerilog and Verilog-AMS.

 

  • Covers the entire Verilog language – using most of it in practice;
  • Provides 27 lab exercises, with complete and tested answers;
  • Explains and emphasizes synthesizability, wherever it pertains to language features;
  • Develops as a major project a synthesizable 70,000-gate SerDes;
  • Presents synthesis-relevant usage of SystemVerilog, and the basic functionality of Verilog-AMS.
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Keywords

Digital Design and Modeling with Verilog System Verilog VLSI Integrated Circuit Design Verilog Hardware Description Language Verilog-AMS

Authors and affiliations

  • John Michael Williams
    • 1
  1. 1.WilsonvilleUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-04789-8
  • Copyright Information Springer International Publishing Switzerland 2014
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-04788-1
  • Online ISBN 978-3-319-04789-8
  • Buy this book on publisher's site