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Euro-Par 2024: Parallel Processing

30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26–30, 2024, Proceedings, Part II

  • Conference proceedings
  • © 2024

Overview

Editors:
  1. Jesus Carretero

    1. University Carlos III of Madrid, Madrid, Spain

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  2. Sameer Shende

    1. University of Oregon, Eugene, USA

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  3. Javier Garcia-Blas

    1. University Carlos III of Madrid, Madrid, Spain

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  4. Ivona Brandic

    1. TU Wien, Vienna, Austria

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  5. Katzalin Olcoz

    1. Universidad Complutense de Madrid, Madrid, Spain

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  6. Martin Schreiber

    1. Université Grenoble Alpes, Saint Martin d'Hères, France

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 14802)

Included in the following conference series:

Conference proceedings info: Euro-Par 2024.

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About this book

The three-volume set LNCS 14801, 14802, and 14803 constitutes the proceedings of the 30th European Conference on Parallel and Distributed Processing, Euro-Par 2024, which took place in Madrid, Spain, during August 26–30, 2024.

The 88 full papers included in the proceedings were carefully reviewed and selected from 293 submissions. They were organized in topical sections as follows:

Part I: Programmind, compilers, and performance; scheduling, resource management, cloud, edge computing, and workflows; 

Part II: Architectures and accelerators; data analytics, AI and computational science; 

Part III: Theory and algorithms; multidisciplinary, domain-specific and applied parallel and distributed computing.

Keywords

Table of contents (33 papers)

  1. Front Matter

    Pages i-xviii
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  2. Architectures and Accelerators

    1. Front Matter

      Pages 1-1
      Download chapter PDF

    2. Efficient RNIC Cache Side-Channel Attack Detection Through DPU-Driven Architecture

      • Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
      Pages 3-17

    3. Parallel Writing of Nested Data in Columnar Formats

      • Jonas Hahnfeld, Jakob Blomer, Thorsten Kollegger
      Pages 18-31

    4. FakeGuard: Novel Architecture Support for Deepfake Detection Networks

      • Xingbin Wang, Dan Meng, Rui Hou, Yan Wang
      Pages 32-46

    5. Exploring Processor Micro-architectures Optimised for BLAS3 Micro-kernels

      • Stepan Nassyr, Dirk Pleiter
      Pages 47-61

    6. Fault Tolerant in the Expand Ad-Hoc Parallel File System

      • Dario Muñoz-Muñoz, Felix Garcia-Carballeira, Diego Camarmas-Alonso, Alejandro Calderon-Mateos, Jesus Carretero
      Pages 62-76Open Access

    7. ImSPU: Implicit Sharing of Computation Resources Between Vector and Scalar Processing Units

      • Hongbing Tan, Xiaowei He, Guichu Sun, Liquan Xiao, Yuanhu Cheng, Jing Zhang et al.
      Pages 77-90

    8. ADE-HGNN: Accelerating HGNNs Through Attention Disparity Exploitation

      • Dengke Han, Meng Wu, Runzhen Xue, Mingyu Yan, Xiaochun Ye, Dongrui Fan
      Pages 91-106

    9. Watt: A Write-Optimized RRAM-Based Accelerator for Attention

      • Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang et al.
      Pages 107-120

    10. Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL

      • Marius Meyer, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela Blott, Christian Plessl
      Pages 121-136Open Access

    11. A Folded Computation-in-Memory Accelerator for Fast Polynomial Multiplication in BIKE

      • Chuhui Wang, Zewen Ye, Haibin Shen, Kejie Huang
      Pages 137-151

    12. (re)Assessing PiM Effectiveness for Sequence Alignment

      • Hamidreza Ramezanikebrya, Matei Ripeanu
      Pages 152-166

    13. MEPAD: A Memory-Efficient Parallelized Direct Convolution Algorithm for Deep Neural Networks

      • Leandro Fiorin, Cristina Silvano
      Pages 167-181

    14. A High-Performance Collective I/O Framework Leveraging Node-Local Persistent Memory

      • Keegan Sanchez, Alex Gavin, Suren Byna, Kesheng Wu, Xuechen Zhang
      Pages 182-195

    15. PCTC: Hardware and Software Co-design for Pruned Capsule Networks on Tensor Cores

      • Mohammad Hafezan, Reza Jahadi, Ehsan Atoofian
      Pages 196-210

    16. Harnessing Data Movement Strategies to Optimize Performance-Energy Efficiency of Oil & Gas Simulations in HPC

      • Pedro Rigon, Brenda Schussler, Alexandre Sardinha, Pedro M. Silva, Fábio Oliveira, Alexandre Carissimi et al.
      Pages 211-225

    17. Compact Parallel Hash Tables on the GPU

      • Steef Hegeman, Daan Wöltgens, Anton Wijs, Alfons Laarman
      Pages 226-241

    18. Hybrid Congestion Control for BXI-Based Interconnection Networks

      • Gabriel Gomez-Lopez, Miguel Sánchez de la Rosa, Jesús Escudero-Sahuquillo, Pedro J. Garcia, Francisco J. Quiles, Pierre-Axel Lagadec
      Pages 242-256

  3. Data Analytics, AI and Computational Science

    1. Front Matter

      Pages 257-257
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Other volumes

  1. Euro-Par 2024: Parallel Processing

  2. Euro-Par 2024: Parallel Processing

  3. Euro-Par 2024: Parallel Processing

Editors and Affiliations

  • University Carlos III of Madrid, Madrid, Spain

    Jesus Carretero, Javier Garcia-Blas

  • University of Oregon, Eugene, USA

    Sameer Shende

  • TU Wien, Vienna, Austria

    Ivona Brandic

  • Universidad Complutense de Madrid, Madrid, Spain

    Katzalin Olcoz

  • Université Grenoble Alpes, Saint Martin d'Hères, France

    Martin Schreiber

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