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Shared-Memory Synchronization

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  • © 2024

Overview

  • Offers a comprehensive survey of shared-memory synchronization, with an emphasis on “systems-level” issues
  • Includes sufficient coverage of architectural details to understand correctness and performance on modern multicores
  • Enables programmers to understand how synchronization is embedded in modern programming languages

Part of the book series: Synthesis Lectures on Computer Architecture (SLCA)

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Table of contents (10 chapters)

Keywords

About this book

This book offers a comprehensive survey of shared-memory synchronization, with an emphasis on “systems-level” issues. It includes sufficient coverage of architectural details to understand correctness and performance on modern multicore machines, and sufficient coverage of higher-level issues to understand how synchronization is embedded in modern programming languages.


The primary intended audience for this book is “systems programmers”—the authors of operating systems, library packages, language run-time systems, concurrent data structures, and server and utility programs. Much of the discussion should also be of interest to application programmers who want to make good use of the synchronization mechanisms available to them, and to computer architects who want to understand the ramifications of their design decisions on systems-level code.

Authors and Affiliations

  • University of Rochester, Rochester, USA

    Michael L. Scott

  • University of Waterloo, Waterloo, Canada

    Trevor Brown

About the authors

MICHAEL L. SCOTT is the Arthur Gould Yates Professor of Engineering and Chair of the Department of Computer Science at the University of Rochester. He received his Ph.D. from the University of Wisconsin–Madison in 1985. His research interests span operating systems, languages, architecture, and tools, with a particular emphasis on parallel and distributed systems. He is best known for work in synchronization algorithms and concurrent data structures, in recognition of which he shared the 2006 SIGACT/SIGOPS Edsger W. Dijkstra Prize. His textbook on programming language design and implementation (Programming Language Pragmatics, fourth edition, Morgan Kaufmann, Dec. 2015) is a standard in the field. He served as General Chair of SOSP in 2003 and as Program Chair of TRANSACT’07, PPoPP ’08, and ASPLOS ’12. He was named a Fellow of the ACM in 2006, of the IEEE in 2010, and of the AAAS in 2021. At the University of Rochester, he received the Robert and Pamela Goergen Award for Distinguished Achievement and Artistry in Undergraduate Teaching in 2001, the Edmund A. Hajim School of Engineering Lifetime Achievement Award in 2018, and the William H. Riker University Award for Graduate Teaching in 2020.



Trevor Brown is an Assistant Professor in the Cheriton School of Computer Science at the University of Waterloo. He completed his Ph.D. under the supervision of Faith Ellen at the University of Toronto in 2017, and conducted postdoctoral studies at the Institute of Science and Technology, Austria, and the Technion, Israel. His research straddles theory and practice, and focuses on the question of how large scale multicore systems can be programmed easily, efficiently and correctly. His specific research interests include concurrent data structures, lock-free synchronization, memory management, transactional memory, and non-volatile memory. At the University of Toronto, he won the Award for Excellence in Teaching Assistance in 2014. He has served multiple times on the Program Committees of ICDCS, PODC, PPoPP, SIROCCO, and SPAA, and was Publication Chair for PPoPP'19. He received the Best Paper Award at PPoPP'20, Best Artifact Awards at PPoPP'21 and PPoPP'22, and Finalist status in the Best Paper competitions at PPoPP'21 and SPAA'22.

Bibliographic Information

  • Book Title: Shared-Memory Synchronization

  • Authors: Michael L. Scott, Trevor Brown

  • Series Title: Synthesis Lectures on Computer Architecture

  • DOI: https://doi.org/10.1007/978-3-031-38684-8

  • Publisher: Springer Cham

  • eBook Packages: Synthesis Collection of Technology (R0)

  • Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2024

  • Hardcover ISBN: 978-3-031-38683-1Published: 31 January 2024

  • Softcover ISBN: 978-3-031-38686-2Due: 24 May 2024

  • eBook ISBN: 978-3-031-38684-8Published: 30 January 2024

  • Series ISSN: 1935-3235

  • Series E-ISSN: 1935-3243

  • Edition Number: 2

  • Number of Pages: XV, 243

  • Number of Illustrations: 54 b/w illustrations, 15 illustrations in colour

  • Topics: Processor Architectures, Circuits and Systems, Computer Hardware

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