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Design of Interconnection Networks for Programmable Logic

  • Guy Lemieux
  • David Lewis

Table of contents

  1. Front Matter
    Pages i-xx
  2. Guy Lemieux, David Lewis
    Pages 1-8
  3. Guy Lemieux, David Lewis
    Pages 9-24
  4. Guy Lemieux, David Lewis
    Pages 25-38
  5. Guy Lemieux, David Lewis
    Pages 39-80
  6. Guy Lemieux, David Lewis
    Pages 81-100
  7. Guy Lemieux, David Lewis
    Pages 101-139
  8. Guy Lemieux, David Lewis
    Pages 141-166
  9. Guy Lemieux, David Lewis
    Pages 167-169
  10. Back Matter
    Pages 171-206

About this book

Introduction

Programmable Logic Devices (PLDs) have become the key implementation medium for the vast majority of digital circuits designed today. While the highest-volume devices are still built with full-fabrication rather than field­ programmability, the trend towards ever fewer ASICs and more FPGAs is clear. This makes the field of PLD architecture ever more important, as there is stronger demand for faster, smaller, cheaper and lower-power programmable logic. PLDs are 90% routing and 10% logic. This book focuses on that 90% that is the programmable routing: the manner in which the programmable wires are connected and the circuit design of the programmable switches themselves. Anyone seeking to understand the design of an FPGA needs to become lit­ erate in the complexities of programmable routing architecture. This book builds on the state-of-the-art of programmable interconnect by providing new methods of investigating and measuring interconnect structures, as well as new programmable switch basic circuits. The early portion of this book provides an excellent survey of interconnec­ tion structures and circuits as they exist today. Lemieux and Lewis then provide a new way to design sparse crossbars as they are used in PLDs, and show that the method works with an empirical validation. This is one of a few routing architecture works that employ analytical methods to deal with the routing archi­ tecture design. The analysis permits interesting insights not typically possible with the standard empirical approach.

Keywords

FPGA Field Programmable Gate Array Programmable Array Logic Transistor VLSI complexity integrated circuit logic metal-oxide-semiconductor transistor system on chip (SoC) tables

Authors and affiliations

  • Guy Lemieux
    • 1
  • David Lewis
    • 2
    • 3
  1. 1.Department of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada
  2. 2.Altera Toronto Technology CentreAltera CorporationCanada
  3. 3.Edward S. Rogers Senior Department of Electrical and Computer EngineeringUniversity of TorontoTorontoCanada

Bibliographic information