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Defect Oriented Testing for CMOS Analog and Digital Circuits

  • Manoj Sachdev

Part of the Frontiers in Electronic Testing book series (FRET, volume 10)

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Manoj Sachdev
    Pages 1-14
  3. Manoj Sachdev
    Pages 95-132
  4. Manoj Sachdev
    Pages 243-296
  5. Manoj Sachdev
    Pages 297-303
  6. Back Matter
    Pages 305-308

About this book

Introduction

Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate.
Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives.
Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field.

`A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.'
... from the Foreword by Vishwani D. Agrawal

Keywords

CMOS Programmable Logic analog circuit design integrated circuit logic model modeling stability

Authors and affiliations

  • Manoj Sachdev
    • 1
  1. 1.Philips ResearchThe Netherlands

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4757-4926-7
  • Copyright Information Springer-Verlag US 1999
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4757-4928-1
  • Online ISBN 978-1-4757-4926-7
  • Series Print ISSN 0929-1296
  • Buy this book on publisher's site