High-Speed Clock Network Design

  • Qing K. Zhu

Table of contents

  1. Front Matter
    Pages i-vii
  2. Qing K. Zhu
    Pages 1-22
  3. Qing K. Zhu
    Pages 23-40
  4. Qing K. Zhu
    Pages 41-56
  5. Qing K. Zhu
    Pages 57-73
  6. Qing K. Zhu
    Pages 75-88
  7. Qing K. Zhu
    Pages 109-124
  8. Qing K. Zhu
    Pages 125-134
  9. Qing K. Zhu
    Pages 135-146
  10. Qing K. Zhu
    Pages 147-161
  11. Qing K. Zhu
    Pages 163-170
  12. Back Matter
    Pages 171-187

About this book

Introduction

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.

Keywords

ASIC Flip-Flop Phase Signal VLSI algorithms computer-aided design (CAD) consumption digital design integrated circuit layers microprocessor network networks simulation

Authors and affiliations

  • Qing K. Zhu
    • 1
  1. 1.Intel CorporationT-RAM Inc.USA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4757-3705-9
  • Copyright Information Springer-Verlag US 2003
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4419-5336-0
  • Online ISBN 978-1-4757-3705-9
  • About this book