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The Verilog® Hardware Description Language

  • Donald E. Thomas
  • Philip R. Moorby

Table of contents

  1. Front Matter
    Pages i-xix
  2. Donald E. Thomas, Philip R. Moorby
    Pages 1-45
  3. Donald E. Thomas, Philip R. Moorby
    Pages 47-79
  4. Donald E. Thomas, Philip R. Moorby
    Pages 81-114
  5. Donald E. Thomas, Philip R. Moorby
    Pages 115-158
  6. Donald E. Thomas, Philip R. Moorby
    Pages 159-188
  7. Donald E. Thomas, Philip R. Moorby
    Pages 189-212
  8. Donald E. Thomas, Philip R. Moorby
    Pages 213-226
  9. Donald E. Thomas, Philip R. Moorby
    Pages 227-239
  10. Donald E. Thomas, Philip R. Moorby
    Pages 241-272
  11. Donald E. Thomas, Philip R. Moorby
    Pages 273-282
  12. Back Matter
    Pages 283-354

About this book

Introduction

XV Acknowledgments xvii Chapter 1 Verilog - A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits II Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Behavioral Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines IS Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment("

Keywords

Advanced VLSI Describing digital systems Formal verification Hardware Logic design and simulation Simulating digital systems Synthesizing digital systems Thomas and Moorby Verification Verilog model modeling

Authors and affiliations

  • Donald E. Thomas
    • 1
  • Philip R. Moorby
    • 2
  1. 1.Carnegie Mellon UniversityUSA
  2. 2.Synapix, Inc.USA

Bibliographic information