Advertisement

Formal Equivalence Checking and Design Debugging

  • Shi-Yu Huang
  • Kwang-Ting (Tim) Cheng

Part of the Frontiers in Electronic Testing book series (FRET, volume 12)

Table of contents

  1. Front Matter
    Pages i-xviii
  2. Introduction

    1. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 1-14
  3. Equivalence Checking

    1. Front Matter
      Pages 15-15
    2. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 17-37
    3. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 39-60
    4. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 61-90
    5. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 91-109
    6. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 111-121
    7. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 123-136
  4. Logic Debugging

    1. Front Matter
      Pages 137-137
    2. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 139-157
    3. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 159-174
    4. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 175-187
    5. Shi-Yu Huang, Kwang-Ting Cheng
      Pages 189-209
  5. Back Matter
    Pages 211-229

About this book

Introduction

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley

Keywords

ASIC RTL algorithms circuit computer-aided design (CAD) debugging diagnosis integrated circuit logic mechanics simulation software verification

Authors and affiliations

  • Shi-Yu Huang
    • 1
  • Kwang-Ting (Tim) Cheng
    • 2
  1. 1.National Semiconductor CorporationUSA
  2. 2.University of CaliforniaSanta BarbaraUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-5693-0
  • Copyright Information Kluwer Academic publishers 1998
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-7606-4
  • Online ISBN 978-1-4615-5693-0
  • Series Print ISSN 0929-1296
  • Buy this book on publisher's site