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Formal Semantics and Proof Techniques for Optimizing VHDL Models

  • Kothanda Umamageswaran
  • Sheetanshu L. Pandey
  • Philip A. Wilsey

Table of contents

  1. Front Matter
    Pages i-xxi
  2. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 1-5
  3. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 7-15
  4. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 17-29
  5. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 31-42
  6. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 43-54
  7. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 55-64
  8. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 65-68
  9. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 69-88
  10. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 89-98
  11. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 99-122
  12. Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 123-125
  13. Back Matter
    Pages 127-158

About this book

Introduction

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Keywords

Hardware Hardwarebeschreibungssprache Mathematica Signal VHDL algorithms logic model semantics simulation

Authors and affiliations

  • Kothanda Umamageswaran
    • 1
  • Sheetanshu L. Pandey
    • 1
  • Philip A. Wilsey
    • 1
  1. 1.University of CincinnatiUSA

Bibliographic information