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Interconnects in VLSI Design

  • Hartmut Grabinski

Table of contents

  1. Front Matter
    Pages i-vii
  2. J. M. Wang, E. S. Kuh
    Pages 1-23
  3. F. Caignet, S. Delmas-Ben-dhia, E. Sicard
    Pages 49-59
  4. L. B. Kenmei, F. Huret, E. Paleczny, P. Kennis, G. Servel, D. Deschacht
    Pages 71-77
  5. I. S. Stievano, I. A. Maio, F. G. Canavero
    Pages 89-100
  6. S. Grivet-Talocia, F. G. Canavero
    Pages 101-117
  7. J. Lescot, J. Haidar, A. Giry, F. Ndagijimana
    Pages 119-131
  8. U. Arz, D. F. Williams, H. Grabinski
    Pages 147-154
  9. Amir Wallrabenstein, Thomas Bierhoff, Andreas Himmler, Elmar Griese, Gerd Mrozynski
    Pages 181-194
  10. H. Zimmermann, T. Heide, A. Ghazi, P. Seegebrecht
    Pages 203-212
  11. K. Kieschnick, H. Zimmermann, H. Pleß, P. Seegebrecht
    Pages 213-220
  12. Elmar Griese, Detlef Krabe, Engelbert Strake
    Pages 221-236

About this book

Introduction

This book presents an updated selection of the most representative contributions to the 2nd and 3rd IEEE Workshops on Signal Propagation on Interconnects (SPI) which were held in Travemtinde (Baltic See Side), Germany, May 13-15, 1998, and in Titisee-Neustadt (Black Forest), Germany, May 19-21, 1999. This publication addresses the need of developers and researchers in the field of VLSI chip and package design. It offers a survey of current problems regarding the influence of interconnect effects on the electrical performance of electronic circuits and suggests innovative solutions. In this sense the present book represents a continua­ tion and a supplement to the first book "Signal Propagation on Interconnects", Kluwer Academic Publishers, 1998. The papers in this book cover a wide area of research directions: Beneath the des­ cription of general trends they deal with the solution of signal integrity problems, the modeling of interconnects, parameter extraction using calculations and measurements and last but not least actual problems in the field of optical interconnects.

Keywords

Analysis CMOS FPGA Field Programmable Gate Array VLSI computer-aided design (CAD) integrated circuit metal-oxide-semiconductor transistor modeling simulation

Editors and affiliations

  • Hartmut Grabinski
    • 1
  1. 1.Universität HannoverGermany

Bibliographic information