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On-Chip Inductance in High Speed Integrated Circuits

  • Yehea I. Ismail
  • Eby G. Friedman

Table of contents

  1. Front Matter
    Pages i-xxii
  2. Yehea I. Ismail, Eby G. Friedman
    Pages 1-11
  3. Yehea I. Ismail, Eby G. Friedman
    Pages 13-39
  4. Yehea I. Ismail, Eby G. Friedman
    Pages 41-72
  5. Yehea I. Ismail, Eby G. Friedman
    Pages 73-79
  6. Yehea I. Ismail, Eby G. Friedman
    Pages 121-145
  7. Yehea I. Ismail, Eby G. Friedman
    Pages 147-158
  8. Yehea I. Ismail, Eby G. Friedman
    Pages 159-175
  9. Yehea I. Ismail, Eby G. Friedman
    Pages 197-213
  10. Yehea I. Ismail, Eby G. Friedman
    Pages 247-256
  11. Yehea I. Ismail, Eby G. Friedman
    Pages 257-260
  12. Back Matter
    Pages 261-303

About this book

Introduction

The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies.
On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively.
On-Chip Inductance in High Speed Integrated Circuits is full of design and analysis techniques for RLC interconnect. These techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance.
On-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.

Keywords

CMOS Counter circuit design computer-aided design (CAD) design process integrated circuit interconnect layers material model network production tables transmission

Authors and affiliations

  • Yehea I. Ismail
    • 1
  • Eby G. Friedman
    • 2
  1. 1.Northwestern UniversityUSA
  2. 2.University of RochesterUSA

Bibliographic information