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Turbo Decoder Architecture for Beyond-4G Applications

  • Book
  • © 2014

Overview

Authors:
  1. Cheng-Chi Wong

    1. Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan

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  2. Hsie-Chia Chang

    1. Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan

    View author publications

    You can also search for this author in PubMed   Google Scholar

  • Offers readers a complete introduction to practical turbo decoder design
  • Describes different design methodologies and explains the trade-offs between performance improvement and overhead
  • Explains modern techniques for state-of-the-art designs
  • Includes simulation and implementation results with respect to various decoder circuit designs
  • Reveals novel approaches to higher operating efficiency of turbo decoders for beyond 4G applications

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Table of contents (5 chapters)

  1. Front Matter

    Pages i-viii
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  2. Introduction

    • Cheng-Chi Wong, Hsie-Chia Chang
    Pages 1-31

  3. Conventional Architecture of Turbo Decoder

    • Cheng-Chi Wong, Hsie-Chia Chang
    Pages 33-51

  4. Turbo Decoder with Parallel Processing

    • Cheng-Chi Wong, Hsie-Chia Chang
    Pages 53-68

  5. Low-Complexity Solution for Highly Parallel Architecture

    • Cheng-Chi Wong, Hsie-Chia Chang
    Pages 69-79

  6. High-Efficiency Solution for Highly Parallel Architecture

    • Cheng-Chi Wong, Hsie-Chia Chang
    Pages 81-96

  7. Back Matter

    Pages 97-100
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Keywords

About this book

This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.

Authors and Affiliations

  • Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan

    Cheng-Chi Wong, Hsie-Chia Chang

Bibliographic Information

  • Book Title: Turbo Decoder Architecture for Beyond-4G Applications

  • Authors: Cheng-Chi Wong, Hsie-Chia Chang

  • DOI: https://doi.org/10.1007/978-1-4614-8310-6

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media New York 2014

  • Hardcover ISBN: 978-1-4614-8309-0

  • Softcover ISBN: 978-1-4939-4742-3

  • eBook ISBN: 978-1-4614-8310-6

  • Edition Number: 1

  • Number of Pages: VIII, 100

  • Number of Illustrations: 33 b/w illustrations, 3 illustrations in colour

  • Topics: Circuits and Systems, Communications Engineering, Networks, Processor Architectures

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